求翻译，一岁宝宝不长牙急急急急

来源：蜘蛛抓取(WebSpider) 时间：2017-04-28 10:36 标签： 北京月嫂招聘急急急
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第三方登录：怀孕病历卡看不懂，求翻译，急急急，求帮助！_百度宝宝知道删除理由：
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求翻译急急急急急急急急急急
发表于&&3条回复&&926次阅读&&&&&&&&
CMOS logic is a newer technology， based on the use of complementary MOS transistors to perform logic functions with almost no current required.This makes these gates very useful in battery-powered applications. The fact that they will work with supply voltages as low as 3 Volts and as high as 15 Volts is also very helpful. CMOS gates are all based on the fundamental inverter circuit shown in Fig. 3.1. Note that both& transistors are enhancement- mode MOSFETs; one N-channel with its source grounded， and one P-channel with its source connected to& ＋V. Their gates are connected together to form the input， and their drains are connected together to form the output. The two MOSFETs are designed to have matching characteristics. Thus， they are complementary to each other. When off， their resistance is
when on， their channel resistance is about 200&O. Since the gate is essentially an open circuit， it draws no current， and the output voltage will be equal to either ground or to the power supply voltage， depending on which transistor is conducting. When input A is grounded (logic 0) ， the N-channel MOSFET is unbiased， and therefore has no channel enhanced within itself. It is an open circuit， and therefore leaves the output line disconnected from ground. At the same time， the P-channel MOSFET is forward biased， so it has a channel enhanced within itself. This channel has a resistance of about 200&O， connecting the output line to the ＋V supply. This pulls the output up to ＋V (logic 1).& When input A is at& ＋V (logic 1) ， the P-channel MOSFET is off and the N-channel MOSFET is on， thus pulling the output down to ground (logic 0). Thus， this circuit correctly performs logic inversion， and at the same time provides active pull-up and pull-down， according to the output state. This concept can be expanded into NOR and NAND structures by combining inverters in a partially series， partially parallel structure. The circuit shown in Fig. 3.2 is a practical example of a CMOS 2-input NOR gate.& In this circuit， if both inputs are low， both P-channel MOSFETs will be turned on， thus providing a connection to ＋V. Both N-channel MOSFETs will be off， so there will be no ground connection. However， if either input goes high， that P-channel MOSFET will turn offand disconnect the output from& ＋V， while that N-channel MOSFET will turn on， thus grounding the output. The structure can be inverted， as shown in Fig. 3.3. Here we have a two-input NAND gate， where a logic 0 at either input will force the output to logic 1， but it takes both inputs at logic 1 to allow the output to go to logic 0.This structure is less limited than the bipolar equivalent would be， but there are still some practical limits. One of these is the combined resistance of the MOSFETs in series. As a result， CMOS totem poles are not made more than four inputs high. Gates with more than four inputs are built as cascading structures rather than single structures. However， the logic is still valid. Even with this limit， the totem pole structure still causes some problems in certain applications. The pull-up and pull-down resistances at the output are never the same， and can change significantly as the inputs change state， even if the output does not change logic states. The result is uneven and unpredictable rise and fall times for the output signal. This problem was addressed， and was solved with the buffered， or B-series CMOS gates. The technique here is to follow the actual NAND gate with a pair of inverters， as shown in Fig. 3.4. Thus， the output will always be driven by a single transistor， either P- channel or N-channel. Since they are as closely matched a
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&&&&&奖励于& 01:42:51
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&如果翻译不了，试试网上在线翻译。
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&&&&&奖励于& 01:18:23
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&&&&& 这是一篇电子技术方面的文章，开头大致是这样的：&&& &CMOS逻辑是一种基于应用互补型MOS晶体管以实现逻辑功能的新技术，这些晶体管几乎不需要电流，因而用这种晶体管构成的门电路非常适合于电池供电的应用场所。&&&&&&&& 翻译起来并不难，发在这个栏内感觉不太合适。&
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&&&&&奖励于& 06:49:29
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帮顶，英文不好！
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&&&&&奖励于& 22:26:38
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:&400-900-8066英语求翻译。。。急急急。。。
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