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Spartan-6 FPGA ConfigurationUser GuideUG380 (v2.7) October 29, 2014Notice of Disclaimer The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available &AS IS& and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditions of Xilinx’s limited warranty, please refer to Xilinx’s Terms of Sale which can be viewed at /legal.htm# IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail- you assume sole risk and liability for use of Xilinx products in such critical applications, please refer to Xilinx’s Terms of Sale which can be viewed at /legal.htm#tos. ? Copyright
Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI, PCI Express, PCIe, and PCI-X are trademarks of PCI-SIG. All other trademarks are the property of their respective owners.Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Revision HistoryThe following table shows the revision history for this document.Date 06/24//2010 Version 1.0 2.0 Initial Xilinx release.Changed REBOOT command to IPROG command throughout the document. Chapter 1: In The High-Speed Priority Option, changed the configuration data size to 3.6 Mb (XC6SLX16). In FPGA Density Migration on page 21, changed the required configuration memory size to 2.6 Mb (XC6SLX9) and 3.6 Mb (XC6SLX16). In Protecting the FPGA Bitstream against Unauthorized Duplication, clarified which Spartan-6 devices have AES decryption logic. Chapter 2: Removed the caution statement following Table 2-1. In Figure 2-2, Figure 2-3, Figure 2-6, Figure 2-7, Figure 2-12, and Figure 2-20, changed VCCO_2 resistor to 2.4 kΩ.; added VFS and VBATT ports, added the SUSPEND pin, and added four notes to the end of the Notes section following each figure. In Figure 2-2 and Figure 2-6, removed “either 2.5V or 3.3V” from note about Spartan-6 FPGA VCCO_2 and the Platform Flash PROM VCCO supply inputs. In Note 12 under Figure 2-12 and Note 10 under Figure 2-20, included PLL lock wait. In Figure 2-2, changed PROGRAM_B pull-up power to VCCO_2. Removed Slave DIN from Figure 2-4. Added sentence about SelectMAP unavailability to the first paragraph of SelectMAP Configuration Interface. Added sentence about toggling to the BUSY description in Table 2-3. In Figure 2-6, added a 4.7 kΩ pull-up to PROGRAM_B. Added BUSY to Note 14 under Figure 2-6. Added “configuration and” to Note 2 under Figure 2-7. Moved placement of Table 2-6 and Table 2-7. Removed mention of Winbond’s SPI flash from Table 2-6. Changed the first paragraph of CSI_B. Revised the RDWR_B section. In Note 1 under Figure 2-9, indicated that CSI_B cannot be deasserted during the sync word. In Figure 2-12, changed 3.3V to VCCO_2. In Master BPI Configuration Interface, updated the devices and packages that do not support the BPI indicated A22 and A23 are not in the CSG225 and added “top boot” to parallel NOR flash. In Table 2-7, removed the reference to the BYTE# port in the HDC and LDC descriptions. In Figure 2-20, connected VCCO_1 and BYTE# to VCCO_1 and added pull-up resistors to FCS_B, FOE_B, and FWE_B. Added Note 5 and 6 after Figure 2-20. Removed note about CCLK being free from reflections to avoid double clocking in Board Layout for Configuration Clock (CCLK). Chapter 4: Changed the last sentence in the first paragraph of ICAP_SPARTAN6. In the first paragraph of STARTUP_SPARTAN6, changed EOS to configuration. Chapter 5: Throughout this chapter, included waiting for PLLs to lock along with DCMs. In Table 5-1, added rows for VFS, VBATT, and RFUSE; added Note 4; and changed pin name CMP_CS_B to CMPCS_B and updated its description. Transferred FPGA I/O Pin Settings During Configuration from Chapter 1 and Reserving Dual-Purpose Configuration Pins (Persist) from Chapter 2. In FPGA I/O Pin Settings During Configuration, indicated that all user I/Os have optional pull-ups. Added Note 3 to Table 5-2. In Table 5-3, added Note 1 and revised Note 2. In Table 5-5, changed the values in the “Total Number of Configuration Bits” column. In Device Power-Up (Step 1), changed the second and third paragraphs and added -4 to the fourth paragraph. In Table 5-11, added VFS and VCCO_5; changed VFS and VBATT deleted “Value” and “Units” added Notes 1, 4, and 5; and updated Note 2 to add VFS. Changed the second paragraph following Figure 5-4. Changed the last paragraph in Check Device ID (Step 5). Added clocking specifics for the sequential state machine in the first paragraph of Startup (Step 8). In Table 5-17, revised the DCM_LOCK description and moved Note 3 text to Startup (Step 8). Added new paragraph after Table 5-17. In Loading the Encryption Key, clarified the type of programming cable and rephrased the last sentence in the last paragraph. Changed the fourth and fifth paragraphs of Loading Encrypted Bitstreams. Added the eFUSE section. In Table 5-22, changed the values under the “Total Bits” column. Revised the GENERAL2 and GENERAL4 descriptions in Table 5-30. In Boot History Status Register (BOOTSTS), changed the description of how this register is reset. In Table 5-48, changed bits 2 and 8 to “Reserved.” In Figure 5-16, added a buffer between DOUT and DIN. Added sentence prior to Figure 5-16 about the new buffer. Added the Bitstream Compression section. Chapter 6: Changed the first paragraph. In Table 6-1, changed the “Configuration Data [15:0]” values for Steps 6 and 12. Changed the step numbers in the first sentence under Table 6-1. Added a sentence on SelectMAP data ordering to the paragraph preceding Figure 6-2. In Figure 6-2, changed the timing diagram. Chapter 7: In MultiBoot Overview, changed the last paragraph and removed the caution statement. Made numerous changes to Fallback Behavior. In Reboot Using ICAP_SPARTAN6, changed “next bitstream” to “MultiBoot bitstream” in the first paragraph and changed step 2 in the sequence of commands. In Table 7-1, swapped the values of the Sync words, made changes in the “Explanation” column, and added Note 1 and Note 2. In Watchdog Timer, changed the first sentence in the first three paragraphs. Chapter 8: On page 138, changed slice to frame in the first bullet, revised the fourth bullet, and removed the bullet about transceiver DRPs not being masked. Chapter 9: Changed Table 9-1.RevisionUG380 (v2.7) October 29, 2014Spartan-6 FPGA Configuration User GuideDate 02/22/2010Version 2.1Revision Changed the supported encryption data widths to x1 and x8 in the Bitstream Encryption section. In the third paragraph of Loading Encrypted Bitstreams, clarified that the configuration bitstream can be delivered in an x1 or x8 data width configuration mode, and indicated that SPI x2 and x4, BPI x16, and SelectMAP x16 bus widths are not supported for encrypted bitstreams. Changed the value of pull-up resistors connected between DONE and VCCO_2 from 2.4 kΩ to 330Ω in Figure 2-2, Figure 2-3, Figure 2-6, Figure 2-7, Figure 2-12, and Figure 2-20. Changed the value of the pull-up the resistor connected between INIT_B and VCCO_2 from 2.4 kΩ to 4.7 kΩ in Figure 2-3 and Figure 2-6. Added ports RDWR_B and CSI_B to FPGA (tied to ground) in Figure 2-6. Added second and third paragraphs about configuration clock frequency to Master Modes. Added introductory sentence and two bullets about SelectMAP considerations to SelectMAP Configuration Interface section. Added sentence about VREF to description of RDWR_B in Table 2-3. Added sentence to first paragraph of CSI_B section indicating that CSI_B should not be deasserted in the middle of a sync word. Reformatted the first paragraph in Master BPI Configuration Interface into one paragraph followed by bullets, and added the bullet indicating the removal of the BPI configuration interface from the XC6SLX25/T devices. Changed “VCCO_0” to “VCCO_2” in Figure 2-22, Figure 2-23, and Figure 2-24. Changed second paragraph in Providing Power section. Added “if Suspend feature is not used” and Note 4 to Table 5-2. Changed table reference from Table 5-4 to Table 5-3 in first paragraph of Configuration Pins section. Added “Dual-Purpose” to Table 5-3 title. Changed “LVCMOS25 8 mA SLOW” to “LVCMOS 8 mA SLOW” in second paragraph of Device Power-Up (Step 1). Changed CCLK Output Delay symbol in Table 5-12 from “TICCK” to “TBPIICCK or TSPIICCK” and added Note 2. Changed “VPOR” to “the recommended operating voltage” in the paragraph following Figure 5-4. Added fourth paragraph about startup waiting for DCMs and PLLs by assigning the LCK_CYCLE option to Startup (Step 8). Removed “DSP” from title in Figure 5-13. Added third bullet to Bitstream Compression section under overall benefits on page 113. Changed “warm boot” to “MultiBoot” in first paragraph of Fallback Behavior section. Added sentence indicating how to generate the bitstream automatically to fourth paragraph of Fallback Behavior section. Added last sentence to Note 2 in Table 7-1. Changed “DCM_WAIT” to “LCK_Cycle” in Additional Memory Space Required for LCK_Cycle section title and text. Removed “66” from the possible values listed in the description for the POST_CRC_FREQ constraint. Removed NCF syntax examples from the Syntax Examples section. Changed “BPI UP” to “BPI” in Figure 9-4. Changed “BPI UP, or BPI Down” to “or BPI“ in Note 7 (Notes relevant to Figure 9-4). Updated description of INIT_B in Table 2-2 and Table 2-3. Added VCCO_2 of 3.3V to Note 16 on page 27, Note 9 on page 29, Note 18 on page 33, and Note 12 on page 35. Added a sentence about deasserting the CSI_B signal to Non-Continuous SelectMAP Data Loading. Updated After Configuration entries for CSO_B and INIT_B in Table 2-6. Updated Notes 11 and 16 on page 43. Updated description of INIT_B in Table 2-7. Updated Note 2 on page 50, and Notes 11 and 18 on page 51. Updated External Configuration Clock for Master Modes. Updated guideline about configuration in master mode in Board Layout for Configuration Clock (CCLK). Updated Note 2 after Table 5-3. In Table 5-5, updated Total Number of Configuration Bits column and added Note 2. Removed -4 speed grade from paragraph before Table 5-11. Added paragraph about external master clock pin after Table 5-17. Updated first paragraph of Bitstream Encryption. Updated RFUSE Pin. Changed bitstream length from 32 to 16 and added list of three types of configuration frames to Configuration Memory Frames. Removed Total Bits column from Table 5-22. Updated Type 2 Packet. Changed direction of RDBK_SIGN in Table 5-30 from R/W to W. Updated description of CRC_EXTSTAT_DISABLE in Table 5-34. Replaced type3 (PCFG) with type2 (IOB) in Frame Length Register. Added new paragraph before Table 5-41. Updated Boot History Status Register (BOOTSTS) and Bitstream Compression. Added readback limitations to Preparing a Design for Readback. Updated steps 7 and 8 in Table 6-2. Removed AES encryption from MultiBoot Overview. Added Note 3 to Table 7-4. Updated first sentence in second paragraph of page 137. Updated first paragraph of POST_CRC_INIT_FLAG. Updated Startup Sequencing (GTS).07/30/20102.207/06/20112.3Spartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Date 06/27/2012Version 2.4Revision Updated bullet about VBATT being tied to VCCAUX or ground in notes 8, 17, 11, 15, and 17 after Figure 2-3, Figure 2-6, Figure 2-7, Figure 2-12, and Figure 2-20 respectively. Updated notes after Figure 2-13. Updated references in SPI Configuration Interface. Updated Master SPI Dual (x2) and Quad (x4) Read Commands. In Master BPI Configuration Interface, updated support of Spartan-6 FPGAs for parallel NOR flash from 512 Mb to 1 Gb and for iMPACT software to program bottom boot parallel NOR flash. Updated note 2 after Figure 2-20. Replaced LVCMOS25 with LVCMOS in External Configuration Clock for Master Modes. Updated Board Layout for Configuration Clock (CCLK). Updated last paragraph of Providing Power. Updated note 1 after Table 5-1. Updated descriptions of VBATT and VFS in Table 5-11. Added note 2 to Figure 5-4. Removed sentence about ID error from Check Device ID (Step 5). Updated description of GTS startup setting after Table 5-16. Added note 3 to Table 5-17. Added SPI x1 to Loading Encrypted Bitstreams. Updated first row of Table 5-21. Updated FAR_MAJ Register and Boot History Status Register (BOOTSTS). Updated first paragraph of Configuration Memory Read Procedure (SelectMAP). Updated first paragraph of Status Register for Fallback and IPROG Reconfiguration. Added CRC Masking. Added POST_CRC_SOURCE to Post_CRC Constraints. Added paragraph about using SPI in a serial daisy-chain configuration to Serial Daisy-Chains. Updated SelectMAP Reconfiguration.01/23/20132.5Updated first bullet in sixth paragraph in Overview. Added Vccaux Level. Removed “XC” from some device references throughout the user guide. Updated Figure 2-2, Figure 2-6, Figure 2-21, Figure 5-15, Figure 8-2, Figure 9-1, Figure 9-2, Figure 9-4, and Figure 9-5. Updated second paragraph in SelectMAP Configuration Interface. Updated second paragraph in Non-Continuous SelectMAP Data Loading. Updated sixth paragraph in Master BPI Configuration Interface. Updated Table 2-7, Table 4-3, Table 5-2, Table 5-19, Table 5-50, Table 6-2, Table 6-5, Table 6-6, and Table 10-4. Added Determining the Maximum Configuration Clock Frequency. Updated first paragraph after Table 2-8. Updated third paragraph in Board Layout for Configuration Clock (CCLK). Updated first paragraph in FPGA I/O Pin Settings During Configuration. Updated pin GCLK0 in Table 5-3. Updated second paragraph in Device Power-Up (Step 1). Updated first paragraph in Cyclic Redundancy Check (Step 7). Updated first paragraph in Startup (Step 8). Updated first and second paragraphs and Table 5-22 in Configuration Memory Frames. Updated third paragraph in Frame Length Register. Updated first paragraph in Identifier Memory Specifications. Updated Steps 3 and 6 in Configuration Register Read Procedure (SelectMAP). Updated Step 13 in Configuration Memory Read Procedure (SelectMAP). Updated first and sixth paragraphs following Figure 7-1. Updated first paragraph and Table 7-4 in Status Register for Fallback and IPROG Reconfiguration. Added Caution after first paragraph in Chapter 8, Readback CRC. Updated first and third bullet and note in CRC Masking. Changed “dynamic” to “distributed” in CLB with LUT Configured as Distributed RAM or Shift Register and in CLBs Near Top or Bottom IOI DRP with LUTs Configured as Distributed RAM. Added second paragraph to Bit Sequence Boundary-Scan Register. Updated first paragraph of CSI_B. Updated Figure 2-20. Updated explanation of O[15:0] in Table 4-2. Updated SUSPEND pin in Table 5-2. Added Caution statement for Bit 16 in Table 5-19. Added paragraph to the end of FPGA I/O Pin Settings During Configuration. Updated first paragraph of Bitstream Overview. Updated Device Power-Up (Step 1). Updated second paragraph of Bitstream Encryption. Updated second paragraph of Loading the Encryption Key. Updated numbered procedure in Configuration Memory Read Procedure (SelectMAP). Added explanation on how to carry out testing when the IOB is configured with an invertor in TAP Controller and Architecture. Updated Steps 5 and 12 in Configuration Memory Read Procedure (SelectMAP). Updated Step 12 in Table 6-2. Minor update to Figure 10-3.06/20/20142.610/29/20142.7UG380 (v2.7) October 29, 2014Spartan-6 FPGA Configuration User GuideSpartan-6 FPGA Configuration User GuideUG380 (v2.7) October 29, 2014Table of ContentsRevision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Preface: About This GuideGuide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Additional Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Chapter 1: Configuration OverviewOverview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16FPGA Configuration Data Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slave Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Basic Configuration Solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Low-Cost Priority Solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The High-Speed Priority Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Conforming to PCI Link Activation Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single and Multiple Configuration Images . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MultiBoot /Safe Update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Required I/O Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Vccaux Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nonvolatile Data Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FPGA Density Migration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Production Lifetime . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Protecting the FPGA Bitstream against Unauthorized Duplication. . . . . . . . . . . . . . . Loading Multiple FPGAs with the Same Configuration Bitstream . . . . . . . . . . . . . . . 16 16 17 18 18 19 19 19 20 20 20 20 20 21 21 21 22Configuration Factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22Chapter 2: Configuration Interface BasicsJTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Serial Configuration Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24Master Serial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Slave Serial Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Serial Configuration Data Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29SelectMAP Configuration Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30Single Device SelectMAP Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Platform Flash PROM SelectMAP Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Microprocessor-Driven SelectMAP Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SelectMAP Data Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CSI_B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RDWR_B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous SelectMAP Data Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Non-Continuous SelectMAP Data Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 32 34 35 35 36 36 36 37Spartan-6 FPGA Configuration User Guide UG380 (v2.7) October 29, 20147SelectMAP Data Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39SPI Configuration Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40Master SPI Vendor Auto-Detection and Error Handling . . . . . . . . . . . . . . . . . . . . . . . . Master SPI Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master SPI Dual (x2) and Quad (x4) Read Commands . . . . . . . . . . . . . . . . . . . . . . . . . Power-On Sequence Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Serial Daisy-Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 45 45 46 47Master BPI Configuration Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47Determining the Maximum Configuration Clock Frequency . . . . . . . . . . . . . . . . . . . . 53 Power-On Sequence Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53External Configuration Clock for Master Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Board Layout for Configuration Clock (CCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54Chapter 3: Boundary-Scan and JTAG ConfigurationIntroduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Boundary-Scan for Spartan-6 Devices Using IEEE Std 1149.1 . . . . . . . . . . . . . . . . . 59Test Access Port (TAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Boundary-Scan Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Using Boundary-Scan in Spartan-6 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62JTAG Signal Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Providing Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Configuring through Boundary-Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63Chapter 4: User PrimitivesBSCAN_SPARTAN6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ICAP_SPARTAN6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STARTUP_SPARTAN6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DNA_PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SUSPEND_SYNC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . POST_CRC_INTERNAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 66 67 67 68 69Chapter 5: Configuration DetailsConfiguration Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71FPGA I/O Pin Settings During Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Reserving Dual-Purpose Configuration Pins (Persist) . . . . . . . . . . . . . . . . . . . . . . . . . . 73Configuration Data File Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Bitstream Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75Sync Word/Bus Width Auto Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76Generating PROM Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77PROM Files for Serial Daisy-Chains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PROM Files for SelectMAP Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PROM Files for SPI/BPI Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bit Swapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel Bus Bit Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Delaying Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 77 77 78 79 80Configuration Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 808Spartan-6 FPGA Configuration User Guide UG380 (v2.7) October 29, 2014Setup (Steps 1-3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device Power-Up (Step 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clear Configuration Memory (Step 2, Initialization) . . . . . . . . . . . . . . . . . . . . . . . . . . . Sample Mode Pins (Step 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bitstream Loading (Steps 4-7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronization (Step 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Check Device ID (Step 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Load Configuration Data Frames (Step 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cyclic Redundancy Check (Step 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Startup (Step 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Advanced Encryption Standard Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating an Encrypted Bitstream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Loading the Encryption Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Loading Encrypted Bitstreams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bitstream Encryption and Internal Configuration Access Port (ICAP) . . . . . . . . . . . . VBATT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . eFUSE Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . eFUSE Control Register (FUSE_CNTL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VFS Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RFUSE Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCCAUX Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 81 83 83 84 84 84 86 86 86 89 89 90 90 91 91 92 92 94 94 94 94Bitstream Encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89eFUSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91Configuration Memory Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Configuration Packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96Packet Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Type 1 Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Type 2 Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 CRC Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 FAR_MAJ Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 FAR_MIN Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 FDRI Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 FDRO Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 MASK Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 EYE_MASK Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 LOUT Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 CBC_REG Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 IDCODE Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 CSBO Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Command Register (CMD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Control Register 0 (CTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Status Register (STAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Configuration Options Register (COR1 and COR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Suspend Register (PWRDN_REG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Frame Length Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Multi-Frame Write Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Configuration Watchdog Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 HC_OPT_REG Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 GENERAL Registers 1, 2, 3, 4, and 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 MODE Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 CCLK_FREQ Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107Spartan-6 FPGA Configuration User Guide UG380 (v2.7) October 29, 20149PU_GWE Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PU_GTS Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Boot History Status Register (BOOTSTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SEU_OPT Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 107 107 108Bitstream Composition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Default Initial Configuration Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Spartan-6 FPGA Unique Device Identifier (Device DNA) . . . . . . . . . . . . . . . . . . . 109Identifier Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Identifier Memory Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Extending Identifier Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG Access to Device Identifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iMPACT Access to Device Identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 110 111 111 112 112Bitstream Compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112Chapter 6: Readback and Configuration VerificationPreparing a Design for Readback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Readback Command Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116Accessing Configuration Registers through the SelectMAP Interface . . . . . . . . . . . . Configuration Register Read Procedure (SelectMAP) . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Memory Read Procedure (SelectMAP) . . . . . . . . . . . . . . . . . . . . . . . . . Accessing Configuration Registers through the JTAG Interface . . . . . . . . . . . . . . . . Configuration Register Read Procedure (JTAG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Memory Read Procedure (IEEE Std 1149.1 JTAG) . . . . . . . . . . . . . . . . . 116 116 118 120 121 123Verifying Readback Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127Chapter 7: Reconfiguration and MultiBootMultiBoot Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Fallback MultiBoot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132Fallback Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132IPROG Reconfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134Reboot Using ICAP_SPARTAN6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134Status Register for Fallback and IPROG Reconfiguration . . . . . . . . . . . . . . . . . . . 135 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Required Data Spacing between MultiBoot Images . . . . . . . . . . . . . . . . . . . . . . . . . 136Flash Sector, Block, or Page Boundaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Additional Memory Space Required for LCK_Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . 136Chapter 8: Readback CRCCRC Masking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138CLB with LUT Configured as Distributed RAM or Shift Register . . . . . . . . . . . . . . . 138 CLBs Near Top or Bottom IOI Using DRP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 CLBs Near Top or Bottom IOI DRP with LUTs Configured as Distributed RAM . . 141Post_CRC Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142POST_CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . POST_CRC_INIT_FLAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . POST_CRC_SOURCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . POST_CRC_ACTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 142 142 14310Spartan-6 FPGA Configuration User Guide UG380 (v2.7) October 29, 2014POST_CRC_FREQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Syntax Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . POST_CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . POST_CRC_INIT_FLAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . POST_CRC_SOURCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . POST_CRC_ACTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . POST_CRC_FREQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143 143 143 143 143 144 144Chapter 9: Advanced Configuration InterfacesSerial Daisy-Chains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Mixed Serial Daisy-Chains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146Guidelines and Design Considerations for Serial Daisy-Chains . . . . . . . . . . . . . . . . Startup Sequencing (GTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Active DONE Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Connect All DONE Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DONE Pin Rise Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bitstream Formatting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 147 147 147 147 147 147 149 151 152 153 153 154 154 155Ganged Serial Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multiple Device SelectMAP Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel Daisy-Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ganged SelectMAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SelectMAP ABORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Configuration Abort Sequence Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Readback Abort Sequence Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ABORT Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Resuming Configuration or Readback After an Abort . . . . . . . . . . . . . . . . . . . . . . . . .SelectMAP Reconfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155Chapter 10: Advanced JTAG ConfigurationsIntroduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 JTAG Configuration/Readback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158TAP Controller and Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Boundary-Scan Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Boundary-Scan Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BYPASS Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Identification (IDCODE) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . USERCODE Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . USER1, USER2, USER3, and USER4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using Boundary-Scan in Spartan-6 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuring through Boundary-Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clocking Startup and Shutdown Sequences (JTAG) . . . . . . . . . . . . . . . . . . . . . . . . . . 158 161 161 162 164 164 164 164 164 165 165 168Spartan-6 FPGA Configuration User Guide UG380 (v2.7) October 29, 20141112Spartan-6 FPGA Configuration User Guide UG380 (v2.7) October 29, 2014PrefaceAbout This GuideThis document describes Spartan?-6 FPGA configuration. Complete and up-to-date documentation of the Spartan-6 family of FPGAs is available on the Xilinx website at /support/documentation/spartan-6.htm.Guide ContentsThis manual contains the following chapters: ? ? ? ? ? ? ? ? ? ? Chapter 1, Configuration Overview Chapter 2, Configuration Interface Basics Chapter 3, Boundary-Scan and JTAG Configuration Chapter 4, User Primitives Chapter 5, Configuration Details Chapter 6, Readback and Configuration Verification Chapter 7, Reconfiguration and MultiBoot Chapter 8, Readback CRC Chapter 9, Advanced Configuration Interfaces Chapter 10, Advanced JTAG ConfigurationsAdditional DocumentationThe following documents are also available for download at: /support/documentation/spartan-6.htm. ? ? Spartan-6 Family Overview This overview outlines the features and product selection of the Spartan-6 family. Spartan-6 FPGA Data Sheet: DC and Switching Characteristics This data sheet contains the DC and Switching Characteristic specifications for the Spartan-6 family. ? Spartan-6 FPGA Packaging and Pinout Specifications This specification includes the tables for device/package combinations and maximum I/Os, pin definitions, pinout tables, pinout diagrams, mechanical drawings, and thermal specifications. ? Spartan-6 FPGA SelectIO Resources User Guide This guide describes the SelectIO? resources available in all Spartan-6 devices.Spartan-6 FPGA Configuration User Guide UG380 (v2.7) October 29, 201413Preface: About This Guide?Spartan-6 FPGA Clocking Resources User Guide This guide describes the clocking resources available in all Spartan-6 devices, including the DCMs and the PLLs.? ?Spartan-6 FPGA Block RAM Resources User Guide This guide describes the Spartan-6 device block RAM capabilities. Spartan-6 FPGA Configurable Logic Blocks User Guide This guide describes the capabilities of the configurable logic blocks (CLBs) available in all Spartan-6 devices.?Spartan-6 FPGA Memory Controller User Guide This guide describes the Spartan-6 FPGA memory controller block, a dedicated, embedded multi-port memory controller that greatly simplifies interfacing Spartan-6 FPGAs to the most popular memory standards.? ?Spartan-6 FPGA GTP Transceivers User Guide This guide describes the GTP transceivers available in Spartan-6 LXT FPGAs. Spartan-6 FPGA DSP48A1 Slice User Guide This guide describes the architecture of the DSP48A1 slice in Spartan-6 FPGAs and provides configuration examples.?Spartan-6 FPGA PCB and Pin Planning Design Guide This guide provides information on PCB design for Spartan-6 devices, with a focus on strategies for making design decisions at the PCB and interface level.?Spartan-6 FPGA Power Management User Guide This guide provides information on the various hardware methods of power management in Spartan-6 devices, primarily focusing on the suspend mode.Additional ResourcesTo find additional documentation, see the Xilinx website at: /support/documentation/index.htm. To search the Answer Database of silicon, software, and IP questions and answers, or to create a technical support WebCase, see the Xilinx website at: /support.14Spartan-6 FPGA Configuration User Guide UG380 (v2.7) October 29, 2014Chapter 1Configuration OverviewOverviewSpartan?-6 FPGAs are configured by loading application-specific configuration data―a bitstream―into internal memory. Spartan-6 FPGAs can load themselves from an external nonvolatile memory device or they can be configured by an external smart source, such as a microprocessor, DSP processor, microcontroller, PC, or board tester. In any case, there are two general configuration datapaths. The first is the serial datapath that is used to minimize the device pin requirements. The second datapath is the 8- or 16-bit datapath used for higher performance or access (or link) to industry-standard interfaces, ideal for external data sources like processors, or x8- or x16-parallel flash memory. Like processors and processor peripherals, Xilinx? FPGAs can be reprogrammed, in system, on demand, an unlimited number of times. Because Xilinx FPGA configuration data is stored in CMOS configuration latches (CCLs), it must be reconfigured after it is powered down. The bitstream is loaded each time into the device through special configuration pins. These configuration pins serve as the interface for a number of different configuration modes: ? ? ? ? ? JTAG configuration mode Master Serial/SPI configuration mode (x1, x2, and x4) Slave Serial configuration mode Master SelectMAP/BPI configuration mode (x8 and x16) Slave SelectMAP configuration mode (x8 and x16)The configuration modes are explained in detail in Chapter 2, Configuration Interface Basics. The specific configuration mode is selected by setting the appropriate level on the mode input pins M[1:0]. The M1 and M0 mode pins should be set at a constant DC voltage level, either through pull-up or pull-down resistors (2.4 kΩ), or tied directly to ground or VCCO_2. The mode pins should not be toggled during or before configuration but can be toggled after. See Chapter 2, Configuration Interface Basics, for the mode pin setting options. The terms Master and Slave refer to the direction of the configuration clock (CCLK): ? In Master configuration modes, the Spartan-6 device drives CCLK from an internal oscillator by default or optional external master clock source GCLK0/USERCCLK. To select the desired frequency, the BitGen -g ConfigRate option is used for the internal oscillator. The default is 2 MHz. The CCLK output frequency varies with process, voltage, and temperature. The data sheet FMCCKTOL specification defines the frequency tolerance. A frequency tolerance of ± 50% means that a ConfigRate setting of 10 could generate a CCLK rate of between 5 MHz and 15 MHz.The BitGen sectionSpartan-6 FPGA Configuration User Guide UG380 (v2.7) October 29, 201415Chapter 1: Configuration Overviewof UG628, Command Line Tools User Guide provides more information. After configuration, the oscillator is turned OFF unless one of these conditions is met: ? ? ? ? SEU detection is used. CFGMCLK in STARTUP primitive is connected. The internal clock source is selected in SUSPEND mode (the oscillator is on only during the WAKEUP sequence). Encryption is enabled.CCLK is a dual-purpose pin. Before configuration, there is no on-chip pull-up. After configuration, it is a user pin unless PERSIST is used. ? In Slave configuration modes, CCLK is an input.The JTAG/boundary-scan configuration interface is always available, regardless of the mode pin settings.Design ConsiderationsTo make an efficient system, it is important to consider which FPGA configuration mode best matches the system’s requirements. Each configuration mode dedicates certain FPGA pins and can temporarily use other pins during configuration only. These non-dedicated pins are then released for general use when configuration is completed. See Chapter 5, Configuration Details. Similarly, the configuration mode can place voltage restrictions on some FPGA I/O banks. Several different configuration options are available, and while the options are flexible, there is often an optimal solution for each system. Several topics must be considered when choosing the best configuration option: overall setup, speed, cost, and complexity.FPGA Configuration Data SourceSpartan-6 FPGAs are designed for maximum flexibility. The FPGA either automatically loads itself with configuration data from a PROM, or another external intelligent device like a processor or microcontroller can download the configuration data to the FPGA.Master ModesThe self-loading FPGA configuration modes, generically called Master modes, as shown in Figure 1-1. The Master modes leverage various types of nonvolatile memories to store the FPGA configuration information. In Master mode, the FPGA configuration bitstream typically resides in nonvolatile memory on the same board, generally external to the FPGA. The FPGA provides a configuration clock signal called CCLK (the source is from either an internal oscillator or an optional external master clock source GCLK0/USERCCLK), and the FPGA controls the configuration process. The configuration clock frequency is user controllable in Master modes, using the BitGen -g ConfigRate option. The default is 2 MHz. Regardless of what option the user selects, the configuration clock in Master mode initially starts at 1 MHz. As the FPGA clocks in the bitstream, it reads in the configuration rate setting and then changes accordingly.16Spartan-6 FPGA Configuration User Guide UG380 (v2.7) October 29, 2014Design ConsiderationsX-Ref Target - Figure 1-1SerialXilinxByte-Wide Platform Flash Parallel NOR Flash CE# OE# WE# BYTE#8/16Spartan-6 FPGA DIN CCLKPROMSpartan-6 FPGA FCS_B FOE_B FWE_BD0 XCFxxS XCFxxP CLK(a) Master Serial/SPI Mode SPI Serial Spartan-6 FPGA MOSI DIN CSO_B CCLKFlashLDC D[7:0] D[15:8] A[n:0]n+1DATA[7:0] DATA[15:8] ADDR[n:0]DATA_IN DATA_OUT SELECT CLOCK(c) Master SelectMAP/BPI Mode with Parallel NOR Flash Xilinx XCFxxP Platform Flash PROM8(b) Master Serial/SPI Mode with SPI FlashSpartan-6 FPGA(1) D[7:0]D[7:0] XCFxxPCCLKCLK(d) Master SelectMAP/BPI ModeNote: The remaining Spartan-6 FPGAs support XCFxxP Platform Flash PROMs via Master SelectMAP mode. The master serial and the master SPI configuration modes are combined and use the same mode selection. The master SelectMAP and the master BPI configuration modes are combined and use the same mode selection.UG380_c1_01_060109Figure 1-1: Master Configuration ModesSlave ModesThe externally controlled loading FPGA configuration modes, generically called Slave modes, are also available with either a serial or byte-wide datapath. In Slave mode, an external “intelligent agent” such as a processor, microcontroller, DSP processor, or tester downloads the configuration image into the FPGA, as shown in Figure 1-2. The advantage of the Slave configuration modes is that the FPGA bitstream can reside almost anywhere in the overall system. The bitstream can reside in flash, onboard, along with the host processor's code. It can reside on a hard disk. It can originate somewhere over a network connection or another type of bridge connection.Spartan-6 FPGA Configuration User Guide UG380 (v2.7) October 29, 201417Chapter 1: Configuration OverviewX-Ref Target - Figure 1-2SerialProcessor, Microcontroller SERIAL_DATA CLOCK Spartan-6 FPGA DIN CCLKSelectMAPProcessor, Microcontroller DATA[15:8] DATA[7:0] SELECT READ/WRITE CLOCK8,16Spartan-6 FPGA D[15:8] D[7:0] CSI_B RDWR_B CCLK(a) Slave Serial Mode JTAG Tester, Processor, Microcontroller DATA_OUT MODE_SELECT CLOCK DATA_INSpartan-6 FPGA TDI TMS TCK TDO (b) JTAG(c) Slave SelectMAP ModeUG380_c1_02_051109Figure 1-2:Slave Configuration ModesThe Slave SelectMAP mode is a simple x8- or x16-bit-wide processor peripheral interface, including a chip-select input and a read/write control input. The Slave Serial mode is extremely simple, consisting only of a clock and serial data input.JTAG ConnectionThe four-wire JTAG interface is common on board testers and debugging hardware. In fact, the Xilinx programming cables for Spartan-6 FPGAs, listed here, use the JTAG interface for prototype download and debugging. Regardless of the configuration mode ultimately used in the application, it is best to also include a JTAG configuration path for easy design development. Also see Chapter 3, Boundary-Scan and JTAG Configuration. ? ? Platform Cable USB II/products/devkits/HW-USB-II-G.htmParallel Cable IV/products/devkits/HW-PC4.htmThe Basic Configuration SolutionBasic options include either Master Serial mode using a Xilinx Platform Flash PROM or a third-party SPI PROM. These solutions use the fewest FPGA pins, have flexible I/O voltage support, and select SPI PROMs are supported by iMPACT, the Xilinx JTAG-based programming software. See iMPACT Help under Software Help: /support/documentation/sw_manuals/xilinx11/isehelp_start.htm.18Spartan-6 FPGA Configuration User Guide UG380 (v2.7) October 29, 2014Design ConsiderationsThe Low-Cost Priority SolutionThe option with the lowest cost varies depending on the specific application. ? If there is spare nonvolatile memory already available in the system, the bitstream image can be stored in system memory. It can even be stored on a hard drive or downloaded remotely over a network connection. If so, one of the downloaded modes should be considered: Slave SelectMAP Mode, Slave Serial Mode, or JTAG. If nonvolatile memory is already required for an application, it is possible to consolidate the memory. For example, the FPGA configuration bitstream(s) can be stored with any processor code for the board. If the processor is a MicroBlaze? embedded processor in the FPGA, the FPGA configuration data and the MicroBlaze processor code can share the same nonvolatile memory device. Spartan-6 FPGAs optionally configure directly from commodity SPI serial flash and parallel NOR flash memories. See Chapter 2, Configuration Interface Basics. Also see XAPP973, Indirect Programming of BPI PROMs with Virtex-5 FPGAs, and XAPP974, Indirect Programming of SPI Serial Flash PROMs with Spartan-3A FPGAs.??The High-Speed Priority OptionSome applications require the logic to be operational within a short time. Certain FPGA configuration modes and methods are faster than others. The configuration time includes the initialization time plus the configuration time. Configuration time depends on the size of the device and speed of the configuration logic. For example, configuring at 33 MHz with a 4-bit data bus, a Spartan-6 XC6SLX16 FPGA requires ~28 ms to receive its 3.6 Mb of configuration data. ? ? At the same clock frequency, parallel configuration modes are inherently faster than the serial modes because they program multiple bits at a time. Configuring a single FPGA is inherently faster than configuring multiple FPGAs in a daisy-chain. In a multi-FPGA design where configuration speed is a concern, each FPGA should be configured separately and in parallel. In Master modes, the FPGA internally generates the CCLK configuration clock signal. By default, the CCLK frequency starts out low but can be increased using the ConfigRate bitstream option. The maximum supported CCLK frequency setting depends on the read specifications for the attached nonvolatile memory. A faster memory enables faster configuration. The FPGA's CCLK output frequency varies with process, voltage, and temperature. The fastest guaranteed configuration rate depends on the slowest guaranteed CCLK frequency, as shown in the Spartan-6 FPGA data sheet. If an external clock is available on the board, it is also possible to configure the FPGA in Slave mode while using Xilinx Platform Flash. If an external clock is available on the board, the FPGA supports the ability to connect and use an external clock source during Master mode configuration. It is also possible to use an external clock source to configure the FPGA in a slave mode while using Xilinx Platform Flash. The external clock source during configuration enables predictable configuration times to be achieved in Master modes as well as Slave modes.??Conforming to PCI Link Activation RequirementsThe PCI? Local Bus Specification, Revision 3.0 (“the PCI specification”) defines a number of power and reset requirements. These requirements, when considered in an FPGA implementation, create several challenges that must be addressed for long term reliabilitySpartan-6 FPGA Configuration User Guide UG380 (v2.7) October 29, 201419Chapter 1: Configuration Overviewand broad interoperability. It is important to consider the link activation time in the PCI application and ensure the FPGA can complete configuration during the specified time. Many third-party flash vendors do not meet these specific time constraints.Single and Multiple Configuration ImagesIn most FPGA applications, the FPGA is loaded only when the system is powered on. However, some applications reload the FPGA multiple times while the system is operating, with different FPGA bitstreams for different functions. For example, the FPGA can be loaded with one bitstream to implement a power-on self-test, followed by a second bitstream with the final application. In many test equipment applications, the FPGA is loaded with different bitstreams to execute hardware-assisted tests. In this way, one smaller FPGA can implement the equivalent functionality of a larger ASIC or gate array device. See Chapter 7, Reconfiguration and MultiBoot, for more information.MultiBoot /Safe UpdateIn advanced applications, multiple bitstream images can be stored. One of the images can be upgraded by the user application, and real-time system upgrades can occur. The system can also recover from any failure booting from the initial image.Required I/O VoltagesThe chosen FPGA configuration mode places some constraints on the FPGA application, specifically the I/O voltage allowed on the FPGA's configuration banks. For example, the SPI or BPI modes leverage third-party flash memory components that are usually 3.3V-only devices (but tolerant to lower voltages). This requires that the I/O voltage on the bank or banks attached to the memory must comply with the input voltage.Vccaux LevelThe Vccaux level is programmable as either 2.5V (default) or 3.3V. The user specifies the value in the tools with the CONFIG VCCAUX=2.5 or CONFIG VCCAUX=3.3 constraint.Nonvolatile Data StorageSome FPGA applications store data in external nonvolatile memory. Spartan-6 FPGAs provide useful enhancements for these applications. ? ? Spartan-6 FPGAs can configure directly from external commodity serial (SPI) or parallel Flash PROMs (BPI). The Flash PROM address, data, and control pins are only borrowed by the FPGA during configuration. After configuration, the FPGA has full read/write control over these pins. The FPGA configuration bitstreams and the application’s nonvolatile data can share the same PROM, reducing overall system cost.?20Spartan-6 FPGA Configuration User Guide UG380 (v2.7) October 29, 2014Design ConsiderationsFPGA Density MigrationThe package footprint and pinouts for Spartan-6 FPGAs are designed to allow migration between different densities within a specific family. Likewise, an FPGA application can store other nonvolatile data in the flash memory, requiring a larger storage device. To support design migration between device densities, sufficient configuration memory must be allowed to cover the largest device in the targeted package. For example, if using the Spartan-6 XC6SLX9 device, enough configuration memory to accommodate 2.6 Mb is required. To allow for migration to the Spartan-6 XC6SLX16 device, 3.6 Mb of configuration memory is required. In downloaded applications, enough space in the memory must be reserved for the largest anticipated, uncompressed FPGA bitstream. In self-loaded applications, a PROM footprint and the associated FPGA configuration mode should be used to facilitate easy migration. For example, Xilinx Platform Flash provides excellent migration between 1 to 4 Mb using the XCFxxS serial family and between 8 to 32 Mb using the XCFxxP parallel family. If an application spans between the two, two separate footprints should be used, one for each Platform Flash subfamily. The XCFxxP Flash family requires a 1.8V core supply voltage input while the XCFxxS requires 3.3V. Both families provide 3.3V I/O. The SPI serial flash vendors offer a wider migration range but do require a multi-package footprint. For example, the Atmel DataFlash SPI serial flash family spans the range of 1 to 64 Mb, using a single footprint that accommodates the JEDEC and EIAJ versions of the 8-pin SOIC package along with the 8-connector CASON package. The Numonyx SPI serial flash has uses a different footprint that uses a combined 8-pin and 16-pin SOIC footprint and is also compatible with devices from multiple SPI flash vendors. Similarly, parallel flash supports a wide density range in a common, multi-vendor package footprint. This overview is pr flash vendors should be consulted for specific details.Production LifetimeAn application’s production lifetime should be considered. Commodity memories generally have a shorter production lifetime than the proprietary Xilinx Platform Flash PROMs. For example, if an industrial application is built that will be manufactured for five years or more, Xilinx Platform Flash PROMs provide better long-term availability. Products with shorter production lifetimes can benefit from the multi-vendor pricing and multi-sourcing of commodity memories.Protecting the FPGA Bitstream against Unauthorized DuplicationLike processor code, the bitstream that defines the FPGA’s functionality loads into the FPGA during power-on. Consequently, this means that an unscrupulous company can capture the bitstream and create an unauthorized copy of the design. Like processors, there are multiple techniques to protect the FPGA bitstream and any intellectual property (IP) cores embedded in the FPGA. One of the most powerful techniques is called authentication, which uses unique device “DNA,” and is described in more detail in Chapter 5, Configuration Details. In addition, the 6SLX75/T, 6SLX100/T, and 6SLX150/T devices also have on-chip Advanced Encryption Standard (AES) decryption logic to provide a high degree of design security.Spartan-6 FPGA Configurat