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This methodology is implemented in charge-pump PLL circuit design,the feasibility and efficiency of the method has been verified.
这种设计方法已应用于一种电荷泵锁相环电路设计中,验证了这种设计方法的可行性和有效性。
Stability Analysis for Three-order Charge-Pump PLL
三阶电荷泵锁相环的稳定性分析
A new formula for caculating the locking-time of 3
rd Order Charge-Pump PLL is presented.
对三阶电荷泵锁相环 ( CPPLL)的锁定时间与环路参数之间的关系进行了深入研究 ,提出了一种计算电荷泵锁相环锁定时间的新方法 ,并给出了锁定时间的计算公式。
Because of the small phase-locked error and big capture scale, Charge-Pump PLL (CPPLL) has been one ofmajor digital PLL products.
电荷泵锁相环(CPPLL)以其锁定相差小和捕获范围大的优点成为当前数字锁相环产品的主流。
In fact, this analysis is also fit to analyze the stability of two-order charge-pump PLL loop by simply setting the value of shunt capacitor of two-order filter to zero.
实际上本分析方法也可以用来分析二阶电荷泵锁相环的稳定性,这只需要假定二阶滤波器中的旁路电容为零即可。
A 300MHz、2.3mW@1.8V、CMOS charge-pump PLL
一个300MHz、2．3mW@1．8V、CMOS电荷泵式锁相环
The second is for 1.25Gbit/s gigabit Ethernet, using modified quadrature clock half-rate phase detector, suitable for traditional charge-pump PLL. It is manufactured in 0.18μm CMOS process and tested, the functions are correct and power dissipation is only about 30mW and output peak-peak jitter is 69ps.
第二个用于1.25Gbit/s千兆以太网,采用改进的正交相位时钟半速鉴相器,适应传统的电荷泵型锁相环结构,采用0.18μm CMOS工艺流片测试,功能完全正确,功耗仅为30mW,输出时钟峰峰值抖动为69ps。
Research of charge-pump PLL has involved and a 5 Gb/s monolithic clock recovery circuit is designed and realized by using 0.18μm CMOS technology. A half rate bang-bang phase detector and a four-phase current-controlled ring oscillator incorporated with a charge-pump build up half-rate PLL architecture.
研究了电荷泵锁相环型时钟恢复电路,提出了采用半速率鉴相器、四相位环形电流控制振荡器、电荷泵和环路滤波器组成的半速率锁相环型时钟恢复电路。 采用0.18μm CMOS工艺实现了5Gb/s单片时钟恢复电路。
I establish the model of the nested-loop PLL based on modern charge-pump PLL.
2．在单个数字式锁相环的基础上，建立了锁相环嵌套环路模型并用数值方法对锁定时间和相位噪声特性进行了仿真。
Then, the principle of Delta-Sigma modulator is presented, especially these two familiar modulators, the MASH modulator and interpolative modulator. Excellence and shortage of them are also compared, the stability analysis of 3-order charge-pump PLL has been deduced.
接着介绍了Delta-Sigma调制器工作原理,分析了小数分频锁相环中两种常见的Delta-Sigma调制器,即MASH型调制器和内插型调制器,并比较了这两种结构的优缺点;
A Novel Charge Pump in PLL
锁相环中的新型电荷泵电路(英文)
Stability Analysis for Three-order Charge-Pump PLL
三阶电荷泵锁相环的稳定性分析
Design of High-performance Charge-pump Circuit in PLL
锁相环高性能电荷泵电路的设计
A Charge Pump with Low Current Mismatching Character in PLL
锁相环中低电流失配电荷泵的设计
Novel Charge Pump Design for Fast Locking Time PLL
一种快速锁定PLL的电荷泵设计
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中国学术期刊(光盘版)电子杂志社肖特基charge pump 1-360文档中心
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肖特基charge pump 1
介绍利用肖特基二极管的电荷泵升压原理肖特基二极管组成的电荷泵多电压输出电路图_电路图-华强电子网Page 1of 3
肖特基二极管组成的电荷泵多电压输出电路图
| 作者: —— | 来源:yangjunjun| 查看: 439次 | 用户关注：
在需要价格便宜的多电源输出的方案或者一个简单的负电压、高电压输出回路的时候, 用二极管和电容组成电荷泵很有用.在不用芯片和电感线圈的情况下,二极管电荷泵能够高效输出上至10mA电流的整数倍的正、负电源电压. 下面就说明基本的二极管电荷泵电路.
1.简单由肖特基二极管(使用体积小而且价格便宜的2- unit封装最适)和陶瓷电容组成.
2.可以输出正、负电压
3.电荷泵动作时高效率
在需要价格便宜的多电源输出的方案或者一个简单的负电压、高电压输出回路的时候, 用二极管和电组成的电荷泵很有用.在不用芯片和电感线圈的情况下,二极管电荷泵能够高效输出上至10mA电流的整数正、负电源电压.
下面就说明基本的二极管电荷泵电路.
1.简单由肖特基二极管(使用体积小而且价格便宜的2- unit封装最合适)和陶瓷电容组成.
2.可以输出正、负电压
3.电荷泵动作时高效率
4.最适合用在DC/DC转换器的辅助电压输出.
图1 基本电路
图2 基本电路(2)
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PLL基本结构及各部分电路的典型电路
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PLL基本结构及各部分电路的典型电路
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more authorsAbstractIn order to provide an efficient test method for PLL which is a mixed-signal circuit widely used in most of SoCs, a novel BIST method is developed. The new BIST uses the change of phase differences generated by selectively alternating the feedback frequency. It provides an efficient structural test, reduces an area overhead and improves the test accessibility.Do you want to read the rest of this article?
CitationsCitations3ReferencesReferences6odes and different test methods. It makes very high area overhead and long test time. The proposed scheme provides simple test accessibility since it uses only an internal clock, F ref for the test. While the proposed method does not cut the loop, all other previous works use broken-loop-type which may cause the distortion of the PLL specification. [4] uses not-broken-loop without considering the divide-by-N, however , the loop should be broken to include the divide-by-N. Consequently, the proposed BIST clearly shows the effectiveness of the fault test, providing a low-cost and highlyeffective BIST solution for structural faults.ABSTRACT: Testing PLLs (phase-locked loops) is becoming an important issue that affects both time-to-market and production cost of electronic systems. Though a PLL is the most common mixed-signal building block, it is very difficult to test due to internal analog blocks and signals. In this paper, we propose a new PLL BIST (built-in self test) using the distorted frequency detector that uses only internal digital signals. The proposed BIST does not need to load any analog nodes of the PLL. Therefore, it provides an efficient defect-oriented structural test scheme, reduced area overhead, and improved test quality compared with previous approaches.Article · Oct 2008 ABSTRACT: This paper presents a low-cost Built-In Self-Test (BIST) scheme, which is based on the principle of parity check code. The proposed circuit is consisted of a XOR network, a frequency decrease module, a BIST controller and a fault detector module. Different from the previous methods of PLL BIST, digital signals from the divide-by-N are grouped as transmission codes, and parity check codes are produced synchronously by the BIST controller. Then the results of parity checking are imported to the fault detector and final test results are generated. Purely digital design flow is adopted and hybrid faults models are used to evaluate the efficiency of the circuit. Experimental results indicates that the proposed method can provide the highest test coverage and lower area overhead, which are 98.3% and 4.2%, respectively.Article · Jul 2012 ABSTRACT: Analog and mixed-signal testing is becoming an important issue that affects both the time-to-market and the product cost of many SoCs. In order to provide an efficient testing method for 865–870 MHz Charge pump phase-locked loop (CP-PLL) which constitutes a mixed-signal circuit a novel BIST method is developed. This BIST can be easily implemented with a test stimulus generator circuit, all existing blocks in CP-PLL and fault evaluation circuit. In order to reduce the chip area overheard, this technique use a selection circuit and one delay cell. The simulation results of the novel technique show high fault coverage 100% like that of our previous testing methods. Thus, it provides an efficient structural test suitable for a production test in terms of an area overhead, a test accessibility, and test time.Conference Paper · Mar 2016 · IEICE Transactions on Electronics Full-text · Article · Apr 2000 Article · Apr 2015 Article · Dec 2008 Data provided are for informational purposes only. Although carefully collected, accuracy cannot be guaranteed. Publisher conditions are provided by RoMEO. Differing provisions from the publisher's actual policy or licence agreement may be applicable.This publication is from a journal that may support self archiving.温馨提示！由于新浪微博认证机制调整，您的新浪微博帐号绑定已过期，请重新绑定！&&|&&
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