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& Verb Tense Tutorial
Verb Tenses
Verb tenses are tools that English
speakers use to talk about the past, present and future in their language. You may find that some English tenses, such as
or , do not have direct translations in your language. That is not a problem. By studying this verb tense tutorial, you will learn to think like a native English speaker. If you prefer to use the verb tense pages as a reference only and do not want to complete the tutorial, .
How to use this tutorial:
1. Prepare for the exercises by reading ,
that you want to practice.
2. Complete the verb tense exercises below. After each exercise, we have included links to the tenses covered. And don't miss our .
3. At the bottom of this page, we have included an
Verb Tense Exercises
EXERCISETOPICS COVERED
Present and Past Tenses with Non-Continuous
Present and Past Tense Review
Cumulative Verb Tense Review
Cumulative Verb Tense Review
Simple Present
Simple Past
Simple Future
I English every day.
Two years ago, I English in England.
If you are having problems, I
you study English.
to study English next year.
Present Continuous
Past Continuous
Future Continuous
English now.
English when you called yesterday.
English when you arrive tonight.
English when you arrive tonight.
Present Perfect
Past Perfect
Future Perfect
English in several
different countries.
a little English before
I moved to the U.S.
every tense by the
time I finish this course.
every tense by the
time I finish this course.
Present Perfect Continuous
Past Perfect Continuous
Future Perfect Continuous
English for five
English for five
years before I moved to the U.S.
English for
over two hours by the time you arrive.
English for
over two hours by the time you arrive.
Notice the organization of the tenses
Take a moment to look at the table above and notice how it is organized. It tells you a lot about how native English speakers understand time. There are four present tenses, four past tenses and four future tenses. Each group contains a simple tense, a continuous tense, a perfect tense and a perfect continuous tense. This is important because these groupings can help you learn and remember how English verb tenses are used in real life. For example, present perfect, past perfect and future perfect are all used in very similar ways. Keep this in mind while reading our .
How can I learn English verb tenses?
It is important to understand that the way native English speakers understand time may be very different from the way you understand time in your native language. For example, Germans often make mistakes with present perfect because it looks like a tense in German, but the tense is used very differently in English. If you need help, our detailed
and exercises will teach you how to think like a native speaker.
Make sure you pay attention to the small details. It is important to learn how
can affect tense usage. English learners should also practice , so they don't have to think about grammar in the middle of a conversation. Similarly, you need to take the time to learn the large number of
in English.
Mastering English verb tenses is all about practice, practice, practice. It's easy if you use our !
How many verb tenses are there?
The answer to this question depends on who you ask. Linguists and language researchers often say that English has : past, present and future. They often refer to simple, continuous, perfect and perfect continuous as "aspects" of each tense.
People who teach English as a foreign language say that : simple present, simple past, simple future, present continuous, past continuous, future continuous, present perfect, past perfect, future perfect, present perfect continuous, past perfect continuous, and future perfect continuous.
It is important to point out that in addition to the 12 tenses listed above, there are additional forms such as , , and , which are used to express time in English. Here at Englishpage.com, we describe 15 verb forms in this Verb Tense Tutorial.
What is the most common mistake English learners make with verb tenses?
The most common mistake English learners make is to use simple present to talk about things that are happening now. Present continuous is not optional in English. Another very common mistake is combining present perfect with specific times such as yesterday or last week. That is not correct in English. And very few English learners master the subtle differences between
in simple future. All of these problems are clearly explained in this tutorial.
What sources should I use to learn English verb tenses?
In addition to Englishpage.com's Verb Tense Tutorial, we recommend that English learners read and watch TV to practice what they have learned. However, while news programs and documentaries are great for vocabulary, they are not good for learning typical verb tense usage. Comedies and dramas with lots of dialogue are best. You want to hear natural spoken English which relates to everyday activities. Many teachers use sitcoms, such as "Friends" or "The Big Bang Theory," to teach verb tenses in class.
Your personal online English school. Learn English at Englishpage.com!LaTeX – Use of math symbols and&equations
March 21, 2008 in
Series on Blogging with LaTeX
This is the 2nd post in the series. Previous one:
This series shows my first experiences with using the . They use a version of the
Many of the examples shown here were adapted from the
article , which is actually about formulas in Math Markup.
Accents – Diacritics
Examples on how to put accents in mathematical expressions:
\acute{a} \grave{a} \hat{a} \tilde{a} \breve{a}
\check{a} \bar{a} \ddot{a} \dot{a}
x’, y”
Superscript and subscript
How to display subscripts and superscripts, indexes and exponents:
Subscripts:
b_{ij} gives
C_{m,n} gives
\delta_{j+k} gives
Superscripts:
a^{j2\pi} gives
x^2_3 gives
C^k_{\mu,\nu} gives
Composition with preceding indexes: {}_1^2 \Psi_3^4 gives
Underlines, overlines and stackings
Includes vectors
\hat a \ \bar b \ \vec c
\overrightarrow{a b} \ \overleftarrow{c d} \ \widehat{d e f}
\overline{g h i} \ \underline{j k l}
\overbrace{ 1+2+\cdots+100 }^{5050}
\underbrace{ a+b+\cdots+z }_{26}
A \xleftarrow{n+\mu-1} B \xrightarrow[T]{n\pm i-1} C
\overset{\alpha}{\omega}
\underset{\mu}{\nu} \overset{\beta}{\underset{\Delta}{\tau}}
\stackrel{\zeta}{\eta}
Sets operations and related symbols.
\notin \varnothing \complement
\subset \subseteq \subsetneq \supset \supseteq \supsetneq
\cap \bigcap \cup \bigcup
\ell \mho \Finv \Re \Im \wp
Others – examples using the calligraphic font (\cal)
and the Greek font
for designating sets:
{\cal A} \setminus {\cal B}
\smallsetminus \omega gives
Logical operators and relations:
\forall \exists \nexists \bar{A} \mid
\And \wedge \vee \neg \to \gets \iff
\bigwedge \bigvee \diamond \lozenge
\vdash \Vdash \vDash \Vvdash \models
\forall p,q \, \exists q \mid \bar{q} \to p
\bigwedge _{x \in A} gives
\bigwedge \limits _{x \notin A}
\bar{A \vee B} = \bar{A} \wedge \bar{B}
A \iff B = A \to B \wedge A \gets B
\bigcap \limits _{i=1}^n \bigcup \limits _{j=1}^n {\cal B}_{i,j}
Obs – the statement \limits shown in the examples above puts the indexes exactly above and / or below the symbol. In the first example, \, is used to put an extra space. .
Several types of operators:
+ \oplus \bigoplus \pm \mp –
\times \otimes \bigotimes \cdot \circ \bullet \bigodot
\star * / \div \frac{1}{2}
\sqrt{2} \sqrt[n]{x}
\nabla \partial x
\dot x \ddot y
\rho = \sqrt{x^2 + y^2} gives
\nabla \phi (x,y) = \frac{\partial \phi}{\partial x} +
\frac{\partial \phi}{\partial y} gives
\nabla^2 \phi (x,y) = \frac{\partial^2 \phi}{\partial x^2} +
\frac{\partial^2 \phi}{\partial y^2} gives
\frac{\partial^2 \phi}{\partial x \partial y} = \frac{\partial^2 \phi}{\partial y \partial x} gives
Relations and definitions
To specify relations, mappings and definitions
\sim \approx \simeq \cong \dot =
& & \le \ge
\lessgtr \lesseqgtr \lesseqqgtr
\equiv \not\equiv \ne \propto
\mapsto \longmapsto
Geometric symbols
\circ \bigcirc \Diamond \Box \triangle
\vartriangle \triangledown \triangleleft \triangleright \vartriangleright \vartriangleleft
\angle \sphericalangle \measuredangle 45^\circ
\perp \mid \nmid
\asymp \parallel
Some more frequent types of arrows (there are many more – see in )
\leftarrow \rightarrow \leftrightarrow \Leftarrow \Rightarrow \Leftrightarrow
\leftarrow \gets \rightarrow \to \not\to \leftrightarrow \longleftarrow \longrightarrow
\rightleftharpoons
\leftleftarrows \leftrightarrows \Lleftarrow \leftarrowtail
\uparrow \downarrow \updownarrow \Uparrow \Downarrow \Updownarrow
Special symbols
Some special symbols. There are many more in
\S \P \% \dagger \ddagger \ldots \cdots
\smile \frown \wr \triangleleft \triangleright \infty \bot \top
\imath \hbar \jmath \surd \ast \amalg \therefore \backepsilon \sharp
Summations, Integrals and Products
Several cases, including limits, sequences and series. Notice in the examples below that when you want to put the limits with the same vertical alignment of the math symbol, you must use the \limits declaration. Otherwise, the limits will be put ahead of the symbol.
\lim \limits_{n \to \infty}x_n
\lim _{n \to \infty}x_n
\sum_{k=1}^N k^2
\sum \limits_{k=1}^N k^2
\prod_{i=1}^N x_i
\prod \limits_{i=1}^N x_i
\coprod_{i=1}^N x_i
\coprod \limits_{i=1}^N x_i
\int_{-N}^{N} e^x\, dx
\int \limits_{-N}^{N} e^x\, dx
\iint_{D}^{W} \, dx\,dy
\iiint_{E}^{V} \, dx\,dy\,dz
\iiiint_{F}^{U} \, dx\,dy\,dz\,dt
\oint_{C} x^3\, dx + 4y^2\, dy
Obs – the declaration \, in the above integrals puts extra spaces between consecutive letters. See more about alignement on this post : .
Binomials only. For matrices, see next post.
\binom{n}{p} = \frac{n!}{p!(n-p)!}
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Comments with LaTeX
To enter math expressions in comments just include your expression written in LaTeX as follows:
"$latex expression $"
Find more in the linkFrom Wikipedia, the free encyclopedia
This article's
does not adequately
key points of its contents. Please consider expanding the lead to
of all important aspects of the article. Please discuss this issue on the article's . (December 2016)
is a brand of
designed, manufactured, and marketed by , targeted at the non-consumer , , and
markets. It was introduced in June 1998. Xeon processors are based on normal desktop-grade CPUs, but have some advanced features such as support for , higher
counts, support for larger amounts of RAM, and larger . Some also support multi-socket systems with 2, 4, or 8 sockets.
Some shortcomings that make Xeon processors unsuitable for most consumer-grade desktop PCs include lower
at the same price point (since servers run more tasks in parallel than desktops, core counts are more important than clock rates), usually an absence of an integrated , and lack of support for . Despite such disadvantages, Xeon processors have always had popularity among desktop users (primarily gamers, and ), mainly due to higher core count potential, and lower price to performance ratio vs. the
in terms of total computing power of all cores. Because most Intel Xeon CPUs lack an integrated , systems built with such integrated GPU lacking processors require a discrete graphics card if a
output is desired.
Intel Xeon is a distinct product line from the similarly-named Intel . The first-generation Xeon Phi is a completely different type of device more comparabl it is designed for a PCI Express slot and is meant to be used as a multi-core coprocessor, like the . In the second generation, Xeon Phi evolved into a main processor more similar to the Xeon. It conforms to the same socket as a Xeon processor and is x86- however, as compared to Xeon, the design point of the Xeon Phi emphasizes more cores with higher memory bandwidth.
Intel Xeon processor family:
1 or 2 Sockets
/E3/E5-1xxx and 2xxx/E7-2xxx series
4 or 8 Sockets
xxx/E7-4xxx and 8xxx series
Code named
# of Cores
Code named
# of Cores
250 nm
180 nm
130 nm
Gallatin MP
90 nm
Paxville MP
65 nm
Clovertown
Kentsfield
45 nm
Wolfdale DP
Harpertown
Dunnington
Nehalem-EP
Bloomfield
Beckton (65xx)
Beckton (75xx)
32 nm
Westmere-EX (E7-2xxx)
Westmere-EX (E7-4xxx/8xxx)
Sandy Bridge-EP
Sandy Bridge-EP (E5-46xx)
22 nm
Ivy Bridge (E3/E5-1xxx/E5-2xxx v2)
Ivy Bridge-EP (E5-46xx v2)
Ivy Bridge-EX (E7-28xx v2)
Ivy Bridge-EX (E7-48xx/88xx v2)
Haswell (E3/E5-1xxx/E5-2xxx v3)
Haswell-EP (E5-46xx v3)
Haswell-EX (E7-48xx/88xx v3)
14 nm
Broadwell (E3/E5-1xxx/E5-2xxx v4)
Skylake-DT (E3 v5)
Skylake-SP
The Xeon brand has been maintained over several generations of x86 and
processors. Older models added the Xeon moniker to the end of the name of their corresponding desktop processor, but more recent models used the name Xeon on its own. The Xeon CPUs generally have more
than their desktop counterparts in addition to multiprocessing capabilities.
Pentium II Xeon[]
450 MHz Pentium II Xeon with 512 KByte L2 cache: The cartridge cover has been removed.
The first Xeon-branded processor was the Pentium II Xeon (code-named "Drake"). It was released in 1998, replacing the
in Intel's server lineup. The Pentium II Xeon was a ""
(and shared the same product code: 80523) with a full-speed 512 kB, 1 MB, or 2 MB . The L2 cache was implemented with custom 512 kB SRAMs developed by Intel. The number of SRAMs depended on the amount of cache. A 512 kB configuration required one SRAM, a 1 MB configuration: two SRAMs, and a 2 MB configuration: four SRAMs on both sides of the PCB. Each SRAM was a 12.90 mm by 17.23 mm (222.21 mm?) die fabricated in a 0.35 um four-layer metal CMOS process and packaged in a cavity-down wire-bonded
(LGA). The additional cache required a larger module and thus the Pentium II Xeon used a larger slot, . It was supported by the
dual-processor workstation
quad- or octo-processor chipset.
Pentium III Xeon[]
In 1999, the
Xeon was replaced by the
Xeon. Reflecting the incremental changes from the Pentium II "" core to the Pentium III "" core, the first Pentium III Xeon, named "Tanner", was just like its predecessor except for the addition of
(SSE) and a few cache controller improvements. The product codes for Tanner mirrored that of Katmai; 80525.
The second version, named "Cascades", was based on the Pentium III "" core. The "Cascades" Xeon used a 133 MHz bus and relatively small 256 kB on-die L2 cache resulting in almost the same capabilities as the
Coppermine processors, which were capable of dual-processor operation but not quad-processor operation.
To improve this situation, Intel released another version, officially also named "Cascades", but often referred to as "Cascades 2 MB". That came in two variants: with 1 MB or 2 MB of L2 cache. Its bus speed was fixed at 100 MHz, though in practice the cache was able to offset this. The product code for Cascades mirrored that of Coppermine; 80526.
In mid-2001, the Xeon brand was introduced ("Pentium" was dropped from the name). The initial variant that used the new , "Foster", was slightly different from the desktop
(""). It was a decent[] chip for workstations, but for server applications it was almost always outperformed by the older Cascades cores with a 2 MB L2 cache and AMD's []. Combined with the need to use expensive , the Foster's sales were somewhat unimpressive[].
At most two Foster processors could be accommodated in a symmetric multiprocessing () system built with a mainstream chipset, so a second version (Foster MP) was introduced with a 1 MB L3 cache and the Jackson
capacity. This improved performance slightly, but not enough to lift it out of third place. It was also priced much higher than the dual-processor (DP) versions. The Foster shared the 80528 product code with Willamette.
In 2002 Intel released a
version of Xeon branded CPU, codenamed "Prestonia". It supported Intel's new Hyper-Threading technology and had a 512 kB L2 cache. This was based on the "" Pentium 4 core. A new server chipset,
(which allowed the use of dual-channel ), was released to support this processor in servers, and soon the bus speed was boosted to 533 MT/s (accompanied by new chipsets: the E7501 for servers and the E7505 for workstations). The Prestonia performed much better than its predecessor and noticeably better than Athlon MP. The support of new features in the E75xx series also gave it a key advantage over the Pentium III Xeon and Athlon MP branded CPUs (both stuck with rather old chipsets), and it quickly became the top-selling server/workstation processor.
"Gallatin"[]
Subsequent to the Prestonia was the "Gallatin", which had an L3 cache of 1 MB or 2 MB. Its Xeon MP version also performed much better than the Foster MP, and was popular in servers. Later experience with the 130 nm process allowed Intel to create the Xeon MP branded Gallatin with 4 MB cache. The Xeon branded Prestonia and Gallatin were designated 80532, like Northwood.
Due to a lack of success with Intel's
and Itanium 2 processors, AMD was able to introduce , a 64-bit extension to the . Intel followed suit by including
(formerly EM64T; it is almost identical to ) in the
version of the Pentium 4 (""), and a Xeon version codenamed "Nocona" with 1 MB L2 cache was released in 2004. Released with it were the E7525 (workstation), E7520 and E7320 (both server) chipsets, which added support for ,
and . The Xeon was noticeably slower than AMD's Opteron, although it could be faster in situations where Hyper-Threading came into play.
A slightly updated core called "Irwindale" was released in early 2005, with 2 MB L2 cache and the ability to have its clock speed reduced during low processor demand. Although it was a bit more competitive than the Nocona had been, independent
showed that AMD's Opteron still outperformed Irwindale. Both of these Prescott-derived Xeons have the product code 80546.
64-bit Xeon MPs were introduced in April 2005. The cheaper "Cranford" was an MP version of Nocona, while the more expensive "Potomac" was a Cranford with 8 MB of L3 cache. Like Nocona and Irwindale, they also have product code 80546.
CPU branded Xeon, codenamed Paxville DP, product code 80551, was released by Intel on 10 October 2005. Paxville DP had , and was a dual-core equivalent of the single-core
(related to the
branded "") with 4 MB of L2 Cache (2 MB per core). The only Paxville DP model released ran at 2.8 GHz, featured an 800 MT/s front side bus, and was produced using a .
An MP-capable version of Paxville DP, codenamed Paxville MP, product code 80560, was released on 1 November 2005. There are two versions: one with 2 MB of L2 Cache (1 MB per core), and one with 4 MB of L2 (2 MB per core). Paxville MP, called the dual-core Xeon 7000-series, was produced using a 90 nm process. Paxville MP clock ranges between 2.67 GHz and 3.0 GHz (model numbers ), with some models having a 667 MT/s FSB, and others having an 800 MT/s FSB.
Clock Frequency
2 × 1 MB
2 × 1 MB
2 × 2 MB
2 × 2 MB
Released on 29 August 2006, the 7100 series, codenamed Tulsa (product code 80550), is an improved version of Paxville MP, built on a 65 nm process, with 2 MB of L2 cache (1 MB per core) and up to 16 MB of L3 cache. It uses . Tulsa was released in two lines: the N-line uses a 667 MT/s FSB, and the M-line uses an 800 MT/s FSB. The N-line ranges from 2.5 GHz to 3.5 GHz (model numbers N), and the M-line ranges from 2.6 GHz to 3.4 GHz (model numbers M). L3 cache ranges from 4 MB to 16 MB across the models.
5000-series "Dempsey"[]
On 23 May 2006, Intel released the dual-core CPU (Xeon branded 5000 series) codenamed Dempsey (product code 80555). Released as the Dual-Core Xeon 5000-series, Dempsey is a
processor produced using a , and is virtually identical to Intel's "" , except for the addition of SMP support, which lets Dempsey operate in dual-processor systems. Dempsey ranges between 2.50 GHz and 3.73 GHz (model numbers ). Some models have a 667 MT/s FSB, and others have a ;MT/s FSB. Dempsey has 4 MB of L2 Cache (2 MB per core). A Medium Voltage model, at 3.2 GHz and ;MT/s FSB (model number 5063), has also been released. Dempsey also introduces a new interface for Xeon processors: , also known as Socket J. Dempsey was the first Xeon core in a long time to be somewhat competitive with its Opteron-based counterparts, although it could not claim a decisive lead in any performance metric – that would have to wait for its successor, the Woodcrest.
Speed (GHz)
L2 Cache (MB)
2 × 2
2 × 2
2 × 2
2 × 2
2 × 2
2 × 2
2 × 2
2 × 2
LV (ULV), "Sossaman"[]
On 14 March 2006, Intel released a dual-core processor codenamed Sossaman and branded as Xeon LV (low-voltage). Subsequently, an ULV (ultra-low-voltage) version was released. The Sossaman was a low-/ultra-low-power and double-processor capable CPU (like ), based on the "" processor, for ultradense non-consumer environment (i.e., targeted at the blade-server and embedded markets), and was rated at a
(TDP) of 31 W (LV: 1.66 GHz, 2 GHz and 2.16 GHz) and 15 W (ULV: 1.66 GHz). As such, it supported most of the same features as earlier Xeons: Virtualization Technology, 667 MT/s front side bus, and dual-core processing, but did not support 64-bit operations, so it could not run 64-bit server software, such as , and therefore was limited to 16 GB of memory. A planned successor, codenamed " MP" was to be a drop-in upgrade to enable Sossaman-based servers to upgrade to 64-bit capability. However, this was abandoned in favour of low-voltage versions of the
processor leaving the Sossaman at a dead-end with no upgrade path.
Speed (GHz)
L2 Cache (MB)
3000-series "Conroe"[]
The 3000 series, codenamed Conroe (product code 80557) dual-core Xeon (branded) CPU, released at the end of September 2006, was the first Xeon for single-CPU operation. The same processor is branded as
and , with varying features disabled. They use
(Socket T), operate on a ;MHz front-side bus, support Enhanced Intel
Technology and Intel Virtualization Technology but do not support Hyper-Threading. Conroe Processors with a number ending in "5" have a ;MT/s FSB.
Speed (GHz)
L2 Cache (MB)
Models marked with a star are not present in Intel's database
3100-series "Wolfdale"[]
The 3100 series, codenamed Wolfdale (product code 80570) dual-core Xeon (branded) CPU, was just a rebranded version of the Intel's mainstream
E5000 processors, featuring the same
and 6 MB of L2 cache. Unlike most Xeon processors, they only support single-CPU operation. They use
(Socket T), operate on a ;MHz front-side bus, support Enhanced Intel
Technology and Intel Virtualization Technology but do not support Hyper-Threading.
Speed (GHz)
L2 Cache (MB)
5100-series "Woodcrest"[]
On 26 June 2006, Intel released the dual-core CPU (Xeon branded 5100 series) codenamed Woodcrest (product code 80556); it was the first Intel
processor to be launched on the market. It is a server and workstation version of the
processor. Intel claims that it provides an 80% boost in performance, while reducing power consumption by 20% relative to the Pentium D.
Most models have a ;MT/s FSB, except for the 5110 and 5120, which have a ;MT/s FSB. The fastest processor (5160) operates at 3.0 GHz. All Woodcrests use
and all except two models have a TDP of 65 W. The 5160 has a TDP of 80 W and the 5148LV (2.33 GHz) has a TDP of 40 W. The previous generation Xeons had a TDP of 130 W. All models support Intel 64 (Intel's x86-64 implementation), the , and , with the "" power management option only on Dual-Core Xeon 5140 or above. Woodcrest has 4 MB of shared L2 Cache.
Speed (GHz)
L2 Cache (MB)
5200-series "Wolfdale-DP"[]
On 11 November 2007, Intel released the dual-core CPU (Xeon branded 5200 series) codenamed Wolfdale-DP (product code 80573). It is built on a
like the desktop Core 2 Duo and Xeon-SP , featuring Intel 64 (Intel's x86-64 implementation), the , and . It is unclear whether the "Demand Based Switching" power management is available on the L5238. Wolfdale has 6 MB of shared L2 Cache.
Speed (GHz)
L2 Cache (MB)
7200-series "Tigerton"[]
The 7200 series, codenamed Tigerton (product code 80564) is an MP-capable processor, similar to the
series, but, in contrast, only one core is active on each silicon chip and the other one is disabled, resulting in a dual-core processor.
Speed (GHz)
L2 Cache (MB)
2 × 4
2 × 4
3200-series "Kentsfield"[]
Intel released relabeled versions of its quad-core (2×2) Core 2 Quad processor as the Xeon 3200-series (product code 80562) on 7 January 2007. The 2 × 2 "quad-core" (dual-die dual-core) comprised two separate dual-core die next to each other in one CPU package. The models are the X3210, X3220 and X3230, running at 2.13 GHz, 2.4 GHz and 2.66 GHz, respectively. Like the 3000-series, these models only support single-CPU operation and operate on a ;MHz front-side bus. It is targeted at the "blade" market. The X3220 is also branded and sold as , the X3230 as Q6700.
Speed (GHz)
L2 Cache (MB)
2 × 4
2 × 4
2 × 4
3300-series "Yorkfield"[]
Intel released relabeled versions of its quad-core
Q9400 and Q9x50 processors as the Xeon 3300-series (product code 80569). This processor comprises two separate dual-core dies next to each other in one CPU package and manufactured in a . The models are the X3320, X3350, X3360, X3370 and X3380, running at 2.50 GHz, 2.66 GHz, 2.83 GHz, 3.0 GHz, and 3.16 GHz, respectively. The L2 cache is a unified 6 MB per die (except for the X3320 with a smaller 3 MB L2 cache per die), and a front-side bus of ;MHz. All models feature Intel 64 (Intel's x86-64 implementation), the , and , as well as "Demand Based Switching".
(product code 80584) variant of these processors are X3323, X3353 and X3363. They have a reduced TDP of 80W and are made for single-CPU
systems instead of , which is used in all other Yorkfield processors. In all other respects, they are identical to their Yorkfield counterparts.
5300-series "Clovertown"[]
A quad-core (2×2) successor of the Woodcrest for DP segment, consisting of two dual-core Woodcrest chips in one package similarly to the dual-core Pentium D branded CPUs (two single-core chips) or the quad-core . All Clovertowns use the
package. The Clovertown has been usually implemented with two Woodcrest dies on a , with 8 MB of L2 cache (4 MB per die). Like Woodcrest, lower models use a ;MT/s FSB, and higher models use a ;MT/s FSB. Intel released Clovertown, product code 80563, on 14 November 2006 with models E5310, E5320, E5335, E5345, and X5355, ranging from 1.6 GHz to 2.66 GHz. All models support: MMX, SSE, SSE2, SSE3, SSSE3, Intel 64, XD bit (an NX bit implementation), . The E and X designations are borrowed from Intel's Core 2 mo an ending of -0 implies a ;MT/s FSB, and an ending of -5 implies a ;MT/s FSB. All models have a TDP of 80 W with the exception of the X5355, which has a TDP of 120 W, and the X5365, which has a TDP of 150 W. A low-voltage version of Clovertown with a TDP of 50 W has a model numbers L5310, L5320 and L GHz, 1.86 GHz and 2.0 GHz respectively). The 3.0 GHz X5365 arrived in July 2007, and became available in the
on 4 April 2007. The X5365 performs up to around 38  in the LINPACK benchmark.
Speed (GHz)
L2 Cache (MB)
2 × 4
2 × 4
2 × 4
2 × 4
2 × 4
2 × 4
2 × 4
2 × 4
2 × 4
5400-series "Harpertown"[]
On 11 November 2007 Intel presented -based Xeons – called Harpertown (product code 80574) – to the public. This family consists of dual die quad-core CPUs manufactured on a
and featuring ;MHz, ;MHz, ;MHz front-side buses, with TDP rated from 40 W to 150 W depending on the model. These processors fit in the
package. All models feature Intel 64 (Intel's x86-64 implementation), the , and . All except the E5405 and L5408 also feature . The supplementary character in front of the model-number represents the thermal rating: an L depicts a TDP of 40 W or 50 W, an E depicts 80 W whereas an X is 120 W TDP or above. The speed of 3.00 GHz comes as four models, two models with 80 W TDP two other models with 120 W TDP with ;MHz or ;MHz front-side bus respectively. The fastest Harpertown is the X5492 whose TDP of 150 W is higher than those of the Prescott-based Xeon DP but having twice as many cores. (The X5482 is also sold under the name "Core 2 Extreme QX9775" for use in the
Intel ;MHz front-side bus Xeon processors will drop into the Intel 5400 (Seaburg) chipset whereas several mainboards featuring the Intel -chipset are enabled to run the processors with a ;MHz front-side bus speed. Seaburg features support for dual PCIe 2.0 x16 slots and up to 128 GB of memory.
Speed (GHz)
L2 Cache (MB)
2 × 6
2 × 6
2 × 6
2 × 6
2 × 6
2 × 6
2 × 6
2 × 6
2 × 6
2 × 6
2 × 6
2 × 6
2 × 6
2 × 6
2 × 6
2 × 6
2 × 6
2 × 6
7300-series "Tigerton"[]
The 7300 series, codenamed Tigerton (product code 80565) is a four-socket (packaged in ) and more capable , consisting of two
Core2 architecture silicon chips on a single ceramic module, similar to Intel's Xeon 5300 series Clovertown processor modules.
The 7300 series uses Intel's Caneland (Clarksboro) platform.
Intel claims the 7300 series Xeons offer more than twice the performance per watt as Intel's previous generation 7100 series. The 7300 series' Caneland chipset provides a point to point interface allowing the full front side bus bandwidth per processor.
The 7xxx series is aimed at the large server market, supporting configurations of up to 32 CPUs per host.
Speed (GHz)
L2 Cache (MB)
7400-series "Dunnington"[]
Dunnington – the last CPU of the Penryn generation and Intel's first
(above two) die – features a single-die six- (or hexa-) core design with three unified 3 MB L2 caches (resembling three merged
dual-core Wolfdale dies), and 96 kB L1 cache (Data) and 16 MB of L3 cache. It features ;MHz , fits into the Tigerton's mPGA604 socket, and is compatible with both the Intel Caneland and IBM X4 chipsets. These processors support DDR2- MHz), and have a maximum
below 130 W. They are intended for blades and other stacked computer systems. Availability was scheduled for the second half of 2008. It was followed shortly by the . Total transistor count is 1.9 billion.
Announced on 15 September 2008.
Speed (GHz)
L3 Cache (MB)
3400-series "Lynnfield"[]
Xeon 3400-series processors based on Lynnfield fill the gap between the previous 3300-series "Yorkfield" processors and the newer 3500-series "Bloomfield". Like Bloomfield, they are quad-core single-package processors based on the , but were introduced almost a year later, in September 2009. The same processors are marketed for mid-range to high-end desktops systems as
and . They have two integrated memory channels as well as
(DMI) links, but no
(QPI) interface.
3400-series "Clarkdale"[]
At low end of the 3400-series is not a Lynnfield but a Clarkdale processor, which is also used in the Core i3-500 and Core i5-600 processors as well as the Celeron G1000 and G6000 Pentium series. A single model was released in March 2010, the Xeon L3406. Compared to all other Clarkdale-based products, this one does not support integrated graphics, but has a much lower thermal design power of just 30 W. Compared to the Lynnfield-based Xeon 3400 models, it only offers two cores.
3500-series "Bloomfield"[]
Bloomfield is the codename for the successor to the Xeon Core microarchitecture, is based on the
and uses the same
manufacturing methods as Intel's . The first processor released with the Nehalem architecture is the desktop , which was released in November 2008. This is the server version for single CPU systems. This is a single-socket Intel Xeon processor. The performance improvements over previous Xeon processors are based mainly on:
Integrated
supporting three memory channels of
UDIMM (Unbuffered) or RDIMM (Registered)
A new point-to-point processor interconnect , replacing the legacy front side bus
Simultaneous multithreading by multiple cores and
(2× per core).
Speed (GHz)
L3 Cache (MB)
QPI speed (GT/s)
DDR3 Clock (MHz)
5500-series "Gainestown"[]
Gainestown or Nehalem-EP, the successor to the Xeon Core microarchitecture, is based on the
and uses the same
manufacturing methods as Intel's . The first processor released with the Nehalem microarchitecture is the desktop , which was released in November 2008. Server processors of the Xeon 55xx range were first supplied to testers in December 2008.
The performance improvements over previous Xeon processors are based mainly on:
Integrated
supporting three memory channels of .
A new point-to-point processor interconnect , replacing the legacy front side bus. Gainestown has two QuickPath interfaces.
(2× per core, starting from 5518), that was already present in pre-Core Duo processors.
Speed (GHz)
L3 Cache (MB)
QPI speed (GT/s)
DDR3 Clock (MHz)
Turbo-Boost
C-series "Jasper Forest"[]
Jasper Forest is a Nehalem-based embedded processor with
connections on-die, core counts from 1 to 4 cores and power envelopes from 23 to 85 watts.
The uni-processor version without QPI comes as LC35xx and EC35xx, while the dual-processor version is sold as LC55xx and EC55xx and uses QPI for communication between the processors. Both versions use a DMI link to communicate with the 3420 that is also used in the 3400-series Lynfield Xeon processors, but use an
package that is otherwise used for processors with QPI but no DMI or PCI Express links. The CPUID code of both Lynnfield and Jasper forest is 106Ex, i.e., family 6, model 30.
P1053 belongs into the same family as the LC35xx series, but lacks some
features that are present in the Xeon version.
-series "Gulftown" & "Westmere-EP"[]
Gulftown or Westmere-EP, a six-core 32 nm architecture -based processor, is the basis for the Xeon 36xx and 56xx series and the -980X. It launched in the first quarter of 2010. The 36xx-series follows the 35xx-series Bloomfield uni-processor model while the 56xx-series follows the 55xx-series Gainestown dual-processor model and both are socket compatible to their predecessors.
Speed (GHz)
L3 Cache (MB)
QPI speed (GT/s)
DDR3 Clock (MHz)
Turbo-Boost
-series "Beckton"[]
Beckton or Nehalem-EX (EXpandable server market) is a Nehalem-based processor with up to eight cores and uses buffering inside the chipset to support up to 16 standard DDR3 DIMMS per CPU socket without requiring the use of FB-DIMMS. Unlike all previous Xeon MP processors, Nehalem-EX uses the new
package, replacing the
used in the previous models, up to Xeon . The 75xx models have four QuickPath interfaces, so it can be used in up-to eight-socket configurations, while the 65xx models are only for up to two sockets. Designed by the Digital Enterprise Group (DEG) Santa Clara and Hudson Design Teams, Beckton is manufactured on the P0;nm) technology. Its launch in March 2010 coincided with that of its direct competitor, AMD's
6xxx "Magny-Cours".
Most models limit the number of cores and QPI links as well as the L3 Cache size in order to get a broader range of products out of the single chip design.
DDR3 Clock
Turbo-Boost
2×4.8 GT/s
2×6.4 GT/s
2×6.4 GT/s
3×4.8 GT/s
3×5.8 GT/s
4×6.4 GT/s
4×5.8 GT/s
4×5.8 GT/s
4×6.4 GT/s
4×5.8 GT/s
4×6.4 GT/s
E7-x8xx-series "Westmere-EX"[]
Westmere-EX is the follow-on to Beckton/Nehalem-EX and the first Intel Chip to have ten CPU cores. The microarchitecture is the same as in the six-core Gulftown/Westmere-EP processor, but it uses the
package like Beckton to support up to eight sockets.
Starting with Westmere-EX, the naming scheme has changed once again, with "E7-xxxx" now signifying the high-end line of Xeon processors using a package that supports larger than two-CPU configurations, formerly the 7xxx series. Similarly, the 3xxx uniprocessor and 5xxx dual-processor series turned into E3-xxxx and E5-xxxx, respectively, for later processors.
E3-12xx-series "Sandy Bridge"[]
The Xeon E3-12xx line of processors, introduced in April 2011, uses the
chips that are also the base for the Core i3/i5/i7-2xxx and Celeron/Pentium Gxxx products using the same
socket, but with a different set of features disabled. Notably, the Xeon variants include support for ,
that are not present on the consumer models, while only some Xeon E3 enable the integrated
that is present on Sandy Bridge. Like its Xeon 3400-series predecessors, the Xeon E3 only supports operation with a single CPU socket and is targeted at entry-level workstations and servers. The CPUID of this processor is 0206A7h, the product code is 80623.
E3-12xx v2-series "Ivy Bridge"[]
Xeon E3-12xx v2 is a minor update of the Sandy Bridge-based E3-12xx, using the 22 nm shrink, and providing slightly better performance while remaining backwards compatible. They were released in May 2012 and mirror the desktop Core i3/i5/i7-3xxx parts.
E5-14xx/24xx series "Sandy Bridge-EN" and E5-16xx/26xx/46xx-series "Sandy Bridge-EP"[]
The Xeon E5-16xx processors follow the previous Xeon -series products as the high-end single-socket platform, using the
package introduced with this processor. They share the Sandy Bridge-E platform with the single-socket Core i7-38xx and i7-39xx processors. The CPU chips have no integrated GPU but eight CPU cores, some of which are disabled in the entry-level products. The Xeon E5-26xx line has the same features but also enables multi-socket operation like the earlier Xeon 5000-series and Xeon 7000-series processors.
E5-14xx v2/24xx v2 series "Ivy Bridge-EN" and E5-16xx v2/26xx v2/46xx v2 series "Ivy Bridge-EP"[]
The Xeon E5 v2 line was an update, released in September 2013 to replace the original Xeon E5 processors with a variant based on the Ivy Bridge shrink. The maximum number of CPU cores was raised to 12 per processor module and the total L3 cache was upped to 30 MB. The consumer version of the Xeon E5-16xx v2 processor is the .
E7-28xx v2/48xx v2/88xx v2 series "Ivy Bridge-EX"[]
The Xeon E7 v2 line was an update, released in February 2014 to replace the original Xeon E7 processors with a variant based on the Ivy Bridge shrink. There was no Sandy Bridge version of these processors.
E3-12xx v3 series "Haswell-WS"[]
Intel Xeon E3-1241 v3 CPU, sitting atop the inside part of its retail box that contains an OEM fan-cooled
Intel Xeon E3-1220 v3 CPU, pin side
Introduced in May 2013, Xeon E3-12xx v3 is the first Xeon series based on the Haswell microarchitecture. It uses the new
socket, which was introduced with the desktop Core i5/i7 Haswell processors, incompatible with the LGA 1155 that was used in Xeon E3 and E3 v2. As before, the main difference between the desktop and server versions is added support for ECC memory in the Xeon-branded parts. The main benefit of the new microarchitecture is better power efficiency.
E5-16xx/26xx v3 series "Haswell-EP"[]
Intel Xeon E5-1650 v3 CPU; its retail box contains no OEM heatsink
Introduced in September 2014, Xeon E5-16xx v3 and Xeon E5-26xx v3 series use the new
socket, which is incompatible with the LGA 2011 socket used by earlier Xeon E5 and E5 v2 generations based on Sandy Bridge and Ivy Bridge microarchitectures. Some of the main benefits of this generation, compared to the previous one, are improved power efficiency, higher core counts, and bigger
(LLCs). Following the already used nomenclature, Xeon E5-26xx v3 series allows dual-socket operation.
One of the new features of this generation is that Xeon E5 v3 models with more than 10 cores support
(COD) operation mode, allowing CPU's multiple columns of cores and LLC slices to be logically divided into what is presented as two
(NUMA) CPUs to the operating system. By keeping data and instructions local to the "partition" of CPU which is processing them, thus decreasing the LLC access latency, COD brings performance improvements to NUMA-aware operating systems and applications.
E7-48xx/88xx v3 series "Haswell-EX"[]
Introduced in May 2015, Xeon E7-48xx v3 and Xeon E7-88xx v3 series provide higher core counts, higher per-core performance and improved reliability features, compared to the previous Xeon E7 v2 generation. Following the usual SKU nomenclature, Xeon E7-48xx v3 and E7-88xx v3 series allow multi-socket operation, supporting up to quad- and eight-socket configurations, respectively. These processors use the LGA 2011 (R1) socket.
Xeon E7-48xx v3 and E7-88xx v3 series contain a quad-channel
(IMC), supporting both DDR3 and DDR4
memory modules through the use of Jordan Creek (DDR3) or Jordan Creek 2 (DDR4) memory buffer chips. Both versions of the memory buffer chip connect to the processor using version 2.0 of the Intel Scalable Memory Interconnect (SMI) interface, while supporting
layouts for improved reliability. Up to four memory buffer chips can be connected to a processor, with up to six DIMM slots supported per each memory buffer chip.
Xeon E7-48xx v3 and E7-88xx v3 series also contain functional bug-free support for
(TSX), which was disabled via a
update in August 2014 for Haswell-E, Haswell-WS (E3-12xx v3) and Haswell-EP (E5-16xx/26xx v3) models, due to a bug that was discovered in the TSX implementation.
E3-12xx v4 series "Broadwell-WS"[]
Introduced in June 2015, Xeon E3-12xx v4 is the first Xeon series based on the Broadwell micro architecture. It uses
socket, which was introduced with the desktop Core i5/i7 Haswell processors. As before, the main difference between the desktop and server versions is added support for ECC memory in the Xeon-branded parts. The main benefit of the new microarchitecture is the new lithography process, which results in better power efficiency.
E3-12xx v5 series "Skylake-WS"[]
Introduced in October 2015, Xeon E3-12xx v5 is the first Xeon series based on the Skylake microarchitecture. It uses new
socket, which was introduced with the desktop Core i5/i7 Skylake processors. Although it uses the same socket as consumer processors, it is limited to the C200 server chipset series and will not work with consumer chipsets like Z170. As before, the main difference between the desktop and server versions is added support for ECC memory in the Xeon-branded parts.
E3-12xx v6 series[]
Introduced in January 2017, Xeon E3-12xx v6 is the first Xeon series based on the Kaby Lake microarchitecture. It uses the same
socket, which was introduced with the desktop Core i5/i7 Skylake processors. As before, the main difference between the desktop and server versions is added support for ECC memory and improved energy efficiency in the Xeon-branded parts.
By 2013 Xeon processors were ubiquitous in supercomputers—more than 80% of the
machines in 2013 used them. For the fastest machines, much of the performance comes from
Intel's entry into that market was the , the first machines using it appeared in June 2012 and by June 2013 it was used in the fastest computer in the world.
The first Xeon-based machines in the top-10 appeared in November 2002, two clusters at
The first Xeon-based machine to be in the first place of the TOP500 was the Chinese A in November 2010, which used a mixed Xeon-Nvidia GPU it was overtaken by the Japanese
in 2012, but the
system using 12-core Xeon E5-2692 processors and
cards occupied the first place in both TOP500 lists of 2013.
system, using eight-core Xeon E5-2680 processors but no accelerator cards, managed fourth place in June 2012 and had dropped to tenth by November 2013
Xeon processor-based systems are among the top 20 fastest systems by memory bandwidth as measured by the STREAM benchmark.
An Intel Xeon virtual SMP system using ScaleMP's Versatile SMP (vSMP) architecture with 128 cores and 1 TB RAM. This system aggregates 16 Stoakley platform (Seaburg chipset) systems with total of 32
processors.
Intel , brand name for family of products using the
architecture
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