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基于BASYS2的地铁售票系统
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你可能喜欢rad10 利用basys2实现十进制加减可逆计数器，拨码开关键SW1为自动 功 ，当 HI VHDL-FPGA-Verilog 238万源代码下载-
&文件名称: rad10
& & & & &&]
&&所属分类:
&&开发工具: VHDL
&&文件大小: 190 KB
&&上传时间:
&&下载次数: 1
&&提 供 者:
&详细说明：利用basys2实现十进制加减可逆计数器，拨码开关键SW1为自动可逆加减功能键，当SW1为HIGH时，计数器实现自动可逆模十加减计数功能，即4个七段数码管上几乎同步显示0―1―2―3―4―…9―8―7―…0―1…的模十自动可逆加减计数结果；当SW1为LOW时，计数器按拨码开关键SW0的选择分别执行加减计数功能。即当SW0为HIGH时，计数器实现模十加计数功能，即4个七段数码管上几乎同步显示0―1―2―3―4―…9――0―1…的模十加计数结果；当SW0为LOW时，计数器实现模十减计数功能，即4个七段数码管上几乎同步显示9―8―7―…―1―0―…9―8―7…的模十减计数结果。-Decimal subtraction use basys2 reversible counter, SW1 DIP switch key for automatic reversible subtraction function keys, when SW1 is HIGH, the counter automatically reversible die ten down counting function, ie almost simultaneously displayed on the four seven-segment LED 0-1-2-3-4- ... 9-8-7- ... 0-1 ... die ten automatic reversible down counting results
when SW1 is LOW, the counter by the DIP switch key SW0 choices were
d plus down counting function. Ten die counting result that when SW0 is HIGH, the counter counts up to achieve mold ten functions, namely almost simultaneously displayed on the four seven-segment LED 0-1-2-3-4- ... 9 0-1 of ...
when SW0 is LOW, the counter counts down ten function realization mode, ie almost simultaneously displayed on the four seven-segment LED 9-8-7- ...-1-0- ... 9-8-7 ... the mold count down ten the results.
文件列表(点击判断是否您需要的文件，如果是垃圾请在下面评价投诉):
&&rad10\iseconfig\rad10.projectmgr&&.....\.........\rad10.xreport&&.....\pa.fromNetlist.tcl&&.....\planAhead.ngc2edif.log&&.....\planAhead_pid2740.debug&&.....\planAhead_pid3152.debug&&.....\planAhead_pid3860.debug&&.....\..........run_1\planAhead.jou&&.....\...............\planAhead.log&&.....\...............\planAhead_run.log&&.....\..............2\planAhead.jou&&.....\...............\planAhead.log&&.....\...............\planAhead_run.log&&.....\...............\rad10.data\cache\rad10_ngc_zx.edif&&.....\...............\..........\.onstrs_1\fileset.xml&&.....\...............\..........\runs\impl_1.psg&&.....\...............\..........\....\runs.xml&&.....\...............\..........\sim_1\fileset.xml&&.....\...............\..........\.ources_1\fileset.xml&&.....\...............\..........\wt\project.wpc&&.....\...............\..........\..\webtalk_pa.xml&&.....\...............\rad10.ppr&&.....\..............3\planAhead.jou&&.....\...............\planAhead.log&&.....\...............\planAhead_run.log&&.....\...............\rad10.data\cache\rad10_ngc_zx.edif&&.....\...............\..........\.onstrs_1\designprops.xml&&.....\...............\..........\.........\fileset.xml&&.....\...............\..........\.........\usercols.xml&&.....\...............\..........\runs\impl_1.psg&&.....\...............\..........\....\runs.xml&&.....\...............\..........\sim_1\fileset.xml&&.....\...............\..........\.ources_1\chipscope.xml&&.....\...............\..........\.........\fileset.xml&&.....\...............\..........\.........\ports.xml&&.....\...............\..........\wt\java_command_handlers.wdf&&.....\...............\..........\..\project.wpc&&.....\...............\..........\..\webtalk_pa.xml&&.....\...............\rad10.ppr&&.....\rad10.bgn&&.....\rad10.bit&&.....\rad10.bld&&.....\rad10.cmd_log&&.....\rad10.drc&&.....\rad10.gise&&.....\rad10.lso&&.....\rad10.ncd&&.....\rad10.ngc&&.....\rad10.ngd&&.....\rad10.ngr&&.....\rad10.pad&&.....\rad10.par&&.....\rad10.pcf&&.....\rad10.prj&&.....\rad10.ptwx&&.....\rad10.stx&&.....\rad10.syr&&.....\rad10.twr&&.....\rad10.twx&&.....\rad10.ucf&&.....\rad10.unroutes&&.....\rad10.ut&&.....\rad10.v&&.....\rad10.xise&&.....\rad10.xpi&&.....\rad10.xst&&.....\rad10_bitgen.xwbt&&.....\rad10_envsettings.html&&.....\rad10_guide.ncd&&.....\rad10_map.map&&.....\rad10_map.mrp&&.....\rad10_map.ncd&&.....\rad10_map.ngm&&.....\rad10_map.xrpt&&.....\rad10_ngdbuild.xrpt&&.....\rad10_pad.csv&&.....\rad10_pad.txt&&.....\rad10_par.xrpt&&.....\rad10_summary.html&&.....\rad10_summary.xml&&.....\rad10_usage.xml&&.....\rad10_xst.xrpt&&.....\usage_statistics_webtalk.html&&.....\webtalk.log&&.....\webtalk_pn.xml&&.....\xlnx_auto_0_xdb\cst.xbcd&&.....\.st\work\hdllib.ref&&.....\...\....\vlg18\rad10.bin&&.....\...\....\work.sdbl&&.....\...\....\work.sdbx&&.....\_ngo\netlist.lst&&.....\.xmsgs\bitgen.xmsgs&&.....\......\map.xmsgs&&.....\......\ngdbuild.xmsgs&&.....\......\par.xmsgs&&.....\......\pn_parser.xmsgs&&.....\......\trce.xmsgs&&.....\......\xst.xmsgs&&.....\xst\dump.xst\rad10.prj\ngx\notopt&&.....\...\........\.........\...\opt
&输入关键字，在本站238万海量源码库中尽情搜索：
&[] - 基于Basys2开发板实现VGA输出，PS/2键盘接入的贪吃蛇游戏，键盘上下左右控制方向，小键盘+键控制速度，小键盘回车开始游戏，空格暂停游戏。
&[] - 利用ALTERA FPGA实现对CF的读写操作->【FPGA/CPLD助学小组】
用ISE，只要能我用串口调试助手发个数据给板子，板子收到并发出这个数据在串口调试助手上显示就行。工程最好有实现代码，ucf和测试代码。。谢谢Puzzle 一个用verilog编写的VGA显示拼图游戏，本程序基于Xilinx的Basys2开发板，图像存储于RO VHDL-FPGA-
238万源代码下载-
&文件名称: Puzzle
& & & & &&]
&&所属分类:
&&开发工具: VHDL
&&文件大小: 11636 KB
&&上传时间:
&&下载次数: 12
&&提 供 者:
&详细说明：一个用verilog编写的VGA显示拼图游戏，本程序基于Xilinx的Basys2开发板，图像存储于ROM中-A VGA display jigsaw puzzle with verilog written, the program is based on the Basys2 Xilinx development boards, the image is stored in ROM
文件列表(点击判断是否您需要的文件，如果是垃圾请在下面评价投诉):
&&Puzzle\.lso&&......\bb.v&&......\ipcore_dir\coregen.cgp&&......\..........\coregen.log&&......\..........\create_Pic.tcl&&......\..........\create_Pic2.tcl&&......\..........\create_Pic3.tcl&&......\..........\create_Pic4.tcl&&......\..........\edit_Pic.tcl&&......\..........\Pic\blk_mem_gen_v7_3_readme.txt&&......\..........\...\doc\blk_mem_gen_v7_3_vinfo.html&&......\..........\...\...\pg058-blk-mem-gen.pdf&&......\..........\...\example_design\Pic_exdes.ucf&&......\..........\...\..............\Pic_exdes.vhd&&......\..........\...\..............\Pic_exdes.xdc&&......\..........\...\..............\Pic_prod.vhd&&......\..........\...\implement\implement.bat&&......\..........\...\.........\implement.sh&&......\..........\...\.........\planAhead_ise.bat&&......\..........\...\.........\planAhead_ise.sh&&......\..........\...\.........\planAhead_ise.tcl&&......\..........\...\.........\xst.prj&&......\..........\...\.........\xst.scr&&......\..........\...\simulation\addr_gen.vhd&&......\..........\...\..........\bmg_stim_gen.vhd&&......\..........\...\..........\bmg_tb_pkg.vhd&&......\..........\...\..........\functional\simcmds.tcl&&......\..........\...\..........\..........\simulate_isim.bat&&......\..........\...\..........\..........\simulate_mti.bat&&......\..........\...\..........\..........\simulate_mti.do&&......\..........\...\..........\..........\simulate_mti.sh&&......\..........\...\..........\..........\simulate_ncsim.sh&&......\..........\...\..........\..........\simulate_vcs.sh&&......\..........\...\..........\..........\ucli_commands.key&&......\..........\...\..........\..........\vcs_session.tcl&&......\..........\...\..........\..........\wave_mti.do&&......\..........\...\..........\..........\wave_ncsim.sv&&......\..........\...\..........\Pic_synth.vhd&&......\..........\...\..........\Pic_tb.vhd&&......\..........\...\..........\random.vhd&&......\..........\...\..........\timing\simcmds.tcl&&......\..........\...\..........\......\simulate_isim.bat&&......\..........\...\..........\......\simulate_mti.bat&&......\..........\...\..........\......\simulate_mti.do&&......\..........\...\..........\......\simulate_mti.sh&&......\..........\...\..........\......\simulate_ncsim.sh&&......\..........\...\..........\......\simulate_vcs.sh&&......\..........\...\..........\......\ucli_commands.key&&......\..........\...\..........\......\vcs_session.tcl&&......\..........\...\..........\......\wave_mti.do&&......\..........\...\..........\......\wave_ncsim.sv&&......\..........\Pic.asy&&......\..........\Pic.gise&&......\..........\Pic.mif&&......\..........\Pic.ncf&&......\..........\Pic.ngc&&......\..........\Pic.sym&&......\..........\Pic.v&&......\..........\Pic.veo&&......\..........\Pic.xco&&......\..........\Pic.xise&&......\..........\...2\blk_mem_gen_v7_3_readme.txt&&......\..........\....\doc\blk_mem_gen_v7_3_vinfo.html&&......\..........\....\...\pg058-blk-mem-gen.pdf&&......\..........\....\example_design\Pic2_exdes.ucf&&......\..........\....\..............\Pic2_exdes.vhd&&......\..........\....\..............\Pic2_exdes.xdc&&......\..........\....\..............\Pic2_prod.vhd&&......\..........\....\implement\implement.bat&&......\..........\....\.........\implement.sh&&......\..........\....\.........\planAhead_ise.bat&&......\..........\....\.........\planAhead_ise.sh&&......\..........\....\.........\planAhead_ise.tcl&&......\..........\....\.........\xst.prj&&......\..........\....\.........\xst.scr&&......\..........\....\simulation\addr_gen.vhd&&......\..........\....\..........\bmg_stim_gen.vhd&&......\..........\....\..........\bmg_tb_pkg.vhd&&......\..........\....\..........\functional\simcmds.tcl&&......\..........\....\..........\..........\simulate_isim.bat&&......\..........\....\..........\..........\simulate_mti.bat&&......\..........\....\..........\..........\simulate_mti.do&&......\..........\....\..........\..........\simulate_mti.sh&&......\..........\....\..........\..........\simulate_ncsim.sh&&......\..........\....\..........\..........\simulate_vcs.sh&&......\..........\....\..........\..........\ucli_commands.key&&......\..........\....\..........\..........\vcs_session.tcl&&......\..........\....\..........\..........\wave_mti.do&&......\..........\....\..........\..........\wave_ncsim.sv&&......\..........\....\..........\Pic2_synth.vhd&&......\..........\....\..........\Pic2_tb.vhd&&......\..........\....\..........\random.vhd&&......\..........\....\..........\timing\simcmds.tcl&&......\..........\....\..........\......\simulate_isim.bat&&......\..........\....\..........\......\simulate_mti.bat&&......\..........\....\..........\......\simulate_mti.do&&......\..........\....\..........\......\simulate_mti.sh&&......\..........\....\..........\......\simulate_ncsim.sh&&......\..........\....\..........\......\simulate_vcs.sh&&......\..........\....\..........\......\ucli_commands.key
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